tile: remove files

pull/3678/head
Victor Julien 6 years ago
parent 3f253cb8c0
commit 6fcd2db043

@ -529,9 +529,6 @@
AC_DEFINE([HAVE_DETECT_DISABLED], [1], [Detection is disabled])
])
# Tilera PCIE logging
AM_CONDITIONAL([BUILD_PCIE_LOGGING], [test ! -z "$TILERA_ROOT"])
# libraries
# zlib
@ -606,16 +603,6 @@
fi
fi
AC_MSG_CHECKING([for Mpipe])
AC_COMPILE_IFELSE(
[AC_LANG_PROGRAM([[#include <gxio/mpipe.h>]])],
[
AC_MSG_RESULT([yes])
AC_DEFINE([HAVE_MPIPE],[1],[mPIPE support is available])
LDFLAGS="$LDFLAGS -lgxpci -lgxio -ltmc"
],
[AC_MSG_RESULT([no])])
#libpcre
AC_ARG_WITH(libpcre_includes,
[ --with-libpcre-includes=DIR libpcre include directory],
@ -2510,7 +2497,7 @@ AC_SUBST(CONFIGURE_LOCALSTATEDIR)
AC_SUBST(CONFIGURE_DATAROOTDIR)
AC_SUBST(PACKAGE_VERSION)
AC_OUTPUT(Makefile src/Makefile rust/Makefile rust/Cargo.toml rust/.cargo/config qa/Makefile qa/coccinelle/Makefile rules/Makefile doc/Makefile doc/userguide/Makefile contrib/Makefile contrib/file_processor/Makefile contrib/file_processor/Action/Makefile contrib/file_processor/Processor/Makefile contrib/tile_pcie_logd/Makefile suricata.yaml etc/Makefile etc/suricata.logrotate etc/suricata.service python/Makefile python/suricata/config/defaults.py ebpf/Makefile)
AC_OUTPUT(Makefile src/Makefile rust/Makefile rust/Cargo.toml rust/.cargo/config qa/Makefile qa/coccinelle/Makefile rules/Makefile doc/Makefile doc/userguide/Makefile contrib/Makefile contrib/file_processor/Makefile contrib/file_processor/Action/Makefile contrib/file_processor/Processor/Makefile suricata.yaml etc/Makefile etc/suricata.logrotate etc/suricata.service python/Makefile python/suricata/config/defaults.py ebpf/Makefile)
SURICATA_BUILD_CONF="Suricata Configuration:
AF_PACKET support: ${enable_af_packet}

@ -1,3 +1,3 @@
SUBDIRS = file_processor tile_pcie_logd
SUBDIRS = file_processor
EXTRA_DIST = suri-graphite

@ -1,339 +0,0 @@
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@ -1,14 +0,0 @@
EXTRA_DIST = LICENSE README
if BUILD_PCIE_LOGGING
bin_PROGRAMS = tile_pcie_logd
tile_pcie_logd_SOURCE = tile_pcie_logd.c
AM_CFLAGS = -std=gnu99 -Wall -Werror -g -O2 -I$(TILERA_ROOT)/include \
-DTILEPCI_HOST
tile_pcie_logd_LDDADD = -pthread
endif

@ -1,38 +0,0 @@
Introduction
------------
This application allows writing files to an x86 host from a TILEncore-Gx
PCIe card. The file name and data are sent over PCIe using the Tilera
Packet Queue API from an aplication running on the Tilera processor.
The original purpose is to write log files from Suricata (Intrusion
Dectection System) on the x86 host's file system.
Running The Logger
------------------
To run the application, set the TILERA_ROOT environment variable to
point to a valide Tilera MDE, then do:
make run
The application should be started before the application on the Tile
side that will be generating the log data.
By default, queue number 0 is used. The --queue_index=N command line
argument can be used to change the queue number.
If more than one TILEncore-Gx PCIe card is installed, the --card=M
argument changes to listening to card M.
Caveats
-------
Due to the fact that the host driver allocates 4MB physically
contiguous memory for the packet queue ring buffer, it is possible
that this allocation could fail on a host whose memory has been
considerably fragmented. If the host program exits with the following
error, reboot the host and run the test again.
Host: Failed to open '/dev/tilegxpci%d/packet_queue/t2h/0': Cannot
allocate memory

@ -1,370 +0,0 @@
/* Copyright (C) 2013-2014 Tilera Corporation.
*
* You can copy, redistribute or modify this Program under the terms of
* the GNU General Public License version 2 as published by the Free
* Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* version 2 along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
/**
* \file
*
* \author Ken Steele, Tilera Corporation <suricata@tilera.com>
* \author Tom DeCanio <decanio.tom@gmail.com>
*
* Host side of PCIe alert logging from Suricata running on a
* TILEncore-Gx card.
*/
#include <stdio.h>
#include <stdlib.h>
#include <sys/mman.h>
#include <sys/ioctl.h>
#include <sys/time.h>
#include <fcntl.h>
#include <malloc.h>
#include <unistd.h>
#include <stdint.h>
#include <string.h>
#include <errno.h>
#include <time.h>
#include <assert.h>
#include <asm/tilegxpci.h>
#define CHECK_SEQ_NUM 1
/* The "/dev/tilegxpci%d" device to be used. */
unsigned int card_index = 0;
unsigned int debug = 0;
/*
* When set, drop all alerts rather than write to file. This is for
* testing performance on a file system that can't write files fast
* enough.
*/
unsigned int drop_alerts = 0;
/* Packet queue index. */
unsigned int queue_index;
/* Prefix added to all file paths sent from PCIe card. */
char * path_prefix = NULL;
/* By default, the host ring buffer is 4MB in size and it consists of
* 1024 entries of 4KB buffers. Modify GXPCI_HOST_PQ_RING_ENTRIES in
* <asm/tilegxpci.h> to change the size of each buffer. To increase
* the total ring buffer size, re-configure the host kernel using
* CONFIG_FORCE_MAX_ZONEORDER.
*/
#ifdef GXPCI_HOST_PQ_SEGMENT_ENTRIES
/* New definitions for MDE 4.1.5 */
#define RING_BUF_ELEMS GXPCI_HOST_PQ_SEGMENT_ENTRIES
#define RING_BUF_ELEM_SIZE (HOST_PQ_SEGMENT_MAX_SIZE / GXPCI_HOST_PQ_SEGMENT_ENTRIES)
#else
/* Definitions prior to MDE 4.1.5 */
#define RING_BUF_ELEMS GXPCI_HOST_PQ_RING_ENTRIES
#define RING_BUF_ELEM_SIZE (HOST_PQ_RING_BUF_MAX_SIZE / GXPCI_HOST_PQ_RING_ENTRIES)
#endif
/*********************************************************************/
/* Host-Side Packet Consumer */
/*********************************************************************/
#define TAIL_UPDATE_LIMIT_ENABLE
#define OP_OPEN 1
#define OP_WRITE 2
#define OP_CLOSE 3
typedef struct {
uint32_t magic;
uint32_t fileno;
uint32_t op;
uint32_t seq;
volatile uint32_t len;
uint32_t next_offset;
char buf[];
} TrioMsg;
typedef struct {
FILE *fd;
} FDesc;
#define MAX_FDESC 1024
static FDesc *fdesc[MAX_FDESC];
void run_pcie_logging(void)
{
char dev_name[40];
int pq_fd;
unsigned int host_ring_buffer_size = RING_BUF_ELEMS * RING_BUF_ELEM_SIZE;
volatile TrioMsg *p;
printf("Waiting for PCIe logging data from card %d on queue %d...\n",
card_index, queue_index);
if (path_prefix) {
printf("PCIe logging into directory: '%s'\n", path_prefix);
fflush(stdout);
}
/* Open the packet queue file. */
snprintf(dev_name, sizeof(dev_name), "/dev/tilegxpci%d/packet_queue/t2h/%d",
card_index, queue_index);
do {
pq_fd = open(dev_name, O_RDWR);
if (pq_fd < 0) {
sleep(1);
}
} while (pq_fd < 0);
/* mmap the register space. */
struct gxpci_host_pq_regs_app* pq_regs =
(struct gxpci_host_pq_regs_app*)
mmap(0, sizeof(struct gxpci_host_pq_regs_app),
PROT_READ | PROT_WRITE,
MAP_SHARED, pq_fd, TILEPCI_PACKET_QUEUE_INDICES_MMAP_OFFSET);
if (pq_regs == MAP_FAILED) {
fprintf(stderr, "Failed to mmap PCIe control registers.\n");
exit(EXIT_FAILURE);
}
/* Configure and allocate the ring buffer for the receive queue. */
tilepci_packet_queue_info_t buf_info;
buf_info.buf_size = RING_BUF_ELEM_SIZE;
int err = ioctl(pq_fd, TILEPCI_IOC_SET_PACKET_QUEUE_BUF, &buf_info);
if (err < 0) {
fprintf(stderr, "Failed TILEPCI_IOC_SET_PACKET_QUEUE_BUF: %s\n",
strerror(errno));
abort();
}
/* On the host side, mmap the receive queue region. */
void* buffer =
mmap(0, host_ring_buffer_size, PROT_READ | PROT_WRITE,
MAP_SHARED, pq_fd, TILEPCI_PACKET_QUEUE_BUF_MMAP_OFFSET);
assert(buffer != MAP_FAILED);
/* On the host side, mmap the queue status. */
struct tlr_pq_status *pq_status =
mmap(0, sizeof(struct tlr_pq_status), PROT_READ | PROT_WRITE,
MAP_SHARED, pq_fd, TILEPCI_PACKET_QUEUE_STS_MMAP_OFFSET);
assert(pq_status != MAP_FAILED);
pq_regs->consumer_index = 0;
uint64_t packet_count = 0;
volatile uint32_t write;
uint32_t read = 0;
#ifdef CHECK_SEQ_NUM
uint32_t expect_seq = 1;
#endif
#ifdef HOST_INTERRUPT_MODE
volatile uint32_t* producer_index = &(pq_status->drv_consumer_index);
#else
volatile uint32_t* producer_index = &(pq_regs->producer_index);
#endif
volatile uint32_t* consumer_index = &(pq_regs->consumer_index);
volatile enum gxpci_chan_status_t* status = &(pq_status->status);
while (1) {
if (*status == GXPCI_CHAN_RESET) {
printf("Tile to Host PCIe logging channel was reset.\n");
fflush(stdout);
return;
}
// Get packets off the ring buffer by accessing the receive queue at
// the new write index.
write = *producer_index;
while (write != read) {
if (*status == GXPCI_CHAN_RESET) {
printf("Tile to Host PCIe logging channel was reset.\n");
fflush(stdout);
return;
}
packet_count++;
p = (TrioMsg *)(buffer + ((read&(RING_BUF_ELEMS-1))*RING_BUF_ELEM_SIZE));
if (debug) {
fprintf(stdout, "got a message\n");
fprintf(stdout, "p->magic: %d\n", p->magic);
fprintf(stdout, "p->fileno: %d\n", p->fileno);
#ifdef CHECK_SEQ_NUM
fprintf(stdout, "p->seq: %d\n", p->seq);
#endif
fprintf(stdout, "p->len: %d\n", p->len);
fprintf(stdout, "p->next_offset: %d\n", p->next_offset);
fprintf(stdout, "p->buf: ");
fwrite(&p->buf, sizeof(char), p->len - offsetof(TrioMsg, buf), stdout);
fprintf(stdout, "\n");
fflush(stdout);
}
#ifdef CHECK_SEQ_NUM
if (p->seq != expect_seq) {
/* Check for a reset before reporting a bad sequence
* number to prevent confusing users. */
if (*status == GXPCI_CHAN_RESET) {
printf("Tile to Host PCIe logging channel was reset.\n");
fflush(stdout);
return;
}
fprintf(stderr, "BAD sequence expected %d got %d\n", expect_seq, p->seq);
return;
}
expect_seq = p->seq + 1;
#endif
switch (p->op) {
case OP_OPEN:
if (p->fileno < MAX_FDESC) {
fdesc[p->fileno] = malloc(sizeof(FDesc));
if (fdesc[p->fileno]) {
char mode[2];
mode[0] = p->buf[0];
mode[1] = '\0';
char *file_name = (char *)&p->buf[1];
if (path_prefix) {
/* Added path_prefix to the start of the
* file name. Added space for '\0' and '\'.
* By default, no prefix is added. */
int new_size = strlen(path_prefix) + strlen(file_name) + 1 + 1;
char *new_name = malloc(new_size);
if (!new_name) {
fprintf(stderr, "Failed to allocate memory for %s/%s\n",
path_prefix, file_name);
return;
}
snprintf(new_name, new_size, "%s/%s",
path_prefix, file_name);
file_name = new_name;
}
if ((fdesc[p->fileno]->fd = fopen(file_name, mode)) == NULL) {
fprintf(stderr, "Could not open %s: %s\n",
file_name, strerror(errno));
} else {
printf("Opened '%s' for logging.\n", file_name);
fflush(stdout);
}
}
} else {
fprintf(stderr, "File number %d exceeds Max of %d\n", p->fileno, MAX_FDESC);
}
break;
case OP_WRITE:
if (drop_alerts) {
/* TODO: Report alert count periodically. */
} else {
if (fdesc[p->fileno] && fdesc[p->fileno]->fd) {
fwrite(&p->buf, sizeof(char),
p->len - offsetof(TrioMsg, buf),
fdesc[p->fileno]->fd);
fflush(fdesc[p->fileno]->fd);
}
}
break;
case OP_CLOSE:
if (fdesc[p->fileno] && fdesc[p->fileno]->fd) {
fclose( fdesc[p->fileno]->fd);
free(fdesc[p->fileno]);
fdesc[p->fileno] = NULL;
}
break;
}
read++;
/* Update the read index register to inform the tile side
* that the packet has been read. */
#ifdef TAIL_UPDATE_LIMIT_ENABLE
if ((packet_count & 0x3f) == 0)
*consumer_index = read;
#else
*consumer_index = read;
#endif
}
}
return;
}
/*
* Match argument list option.
* Options ending in '=' take an additional value, which may be
* attached in the same argument or detached in the following
* argument.
* @param arglist Points to remaining argv, updated on match.
* @param option The option to match, ending in '=' if it takes a value.
* @return Value if option matches, NULL otherwise.
*/
char *shift_option(char ***arglist, const char* option)
{
char** args = *arglist;
char* arg = args[0], **rest = &args[1];
int optlen = strlen(option);
char* val = arg+optlen;
if (option[optlen - 1] != '=') {
if (strcmp(arg, option))
return NULL;
} else {
if (strncmp(arg, option, optlen-1))
return NULL;
if (arg[optlen- 1 ] == '\0')
val = *rest++;
else if (arg[optlen - 1] != '=')
return NULL;
}
*arglist = rest;
return val;
}
int main(int argc, char** argv)
{
char **args = &argv[1];
/*
* Scan command line options.
*/
while (*args) {
char* opt = NULL;
if ((opt = shift_option(&args, "--queue_index=")))
queue_index = strtoul(opt, NULL, 0);
else if ((opt = shift_option(&args, "--card=")))
card_index = strtoul(opt, NULL, 0);
else if ((opt = shift_option(&args, "--debug")))
debug = 1;
else if ((opt = shift_option(&args, "--drop")))
drop_alerts = 1;
else if ((opt = shift_option(&args, "--prefix=")))
path_prefix = opt;
else {
fprintf(stderr, "Unknown option '%s'.\n", args[0]);
exit(EXIT_FAILURE);
}
}
run_pcie_logging();
return 0;
}

@ -223,10 +223,6 @@
Enable packet capture using the Napatech Streams API.
.. option:: --mpipe
Enable packet capture using the TileGX mpipe interface.
.. option:: --erf-in=<file>
Run in offline mode reading the specific ERF file (Endace

@ -348,7 +348,6 @@ runmode-pcap-file.c runmode-pcap-file.h \
runmode-pfring.c runmode-pfring.h \
runmode-unittests.c runmode-unittests.h \
runmode-unix-socket.c runmode-unix-socket.h \
runmode-tile.c runmode-tile.h \
runmode-windivert.c runmode-windivert.h \
runmodes.c runmodes.h \
rust.h \
@ -356,7 +355,6 @@ source-af-packet.c source-af-packet.h \
source-erf-dag.c source-erf-dag.h \
source-erf-file.c source-erf-file.h \
source-ipfw.c source-ipfw.h \
source-mpipe.c source-mpipe.h \
source-napatech.c source-napatech.h \
source-netmap.c source-netmap.h \
source-nfq.c source-nfq.h \
@ -375,7 +373,7 @@ stream-tcp-reassemble.c stream-tcp-reassemble.h \
stream-tcp-sack.c stream-tcp-sack.h \
stream-tcp-util.c stream-tcp-util.h \
suricata.c suricata.h \
threads.c threads.h threads-arch-tile.h \
threads.c threads.h \
threads-debug.h threads-profile.h \
tm-modules.c tm-modules.h \
tmqh-flow.c tmqh-flow.h \
@ -429,7 +427,6 @@ util-ioctl.h util-ioctl.c \
util-ip.h util-ip.c \
util-ja3.h util-ja3.c \
util-logopenfile.h util-logopenfile.c \
util-logopenfile-tile.h util-logopenfile-tile.c \
util-log-redis.h util-log-redis.c \
util-lua.c util-lua.h \
util-luajit.c util-luajit.h \

@ -62,7 +62,6 @@ enum PktSrcEnum {
#include "source-ipfw.h"
#include "source-pcap.h"
#include "source-af-packet.h"
#include "source-mpipe.h"
#include "source-netmap.h"
#include "source-windivert.h"
#ifdef HAVE_PF_RING_FLOW_OFFLOAD
@ -463,10 +462,6 @@ typedef struct Packet_
#ifdef AF_PACKET
AFPPacketVars afp_v;
#endif
#ifdef HAVE_MPIPE
/* tilegx mpipe stuff */
MpipePacketVars mpipe_v;
#endif
#ifdef HAVE_NETMAP
NetmapPacketVars netmap_v;
#endif
@ -609,12 +604,7 @@ typedef struct Packet_
#ifdef HAVE_NAPATECH
NapatechPacketVars ntpv;
#endif
}
#ifdef HAVE_MPIPE
/* mPIPE requires packet buffers to be aligned to 128 byte boundaries. */
__attribute__((aligned(128)))
#endif
Packet;
} Packet;
/** highest mtu of the interfaces we monitor */
extern int g_default_mtu;

@ -506,11 +506,6 @@ uint16_t PatternMatchDefaultMatcher(void)
}
done:
#ifdef __tile__
if (mpm_algo_val == MPM_AC)
mpm_algo_val = MPM_AC_KS;
#endif
return mpm_algo_val;
}

@ -289,19 +289,9 @@ typedef struct FlowAddress_ {
#define addr_data16 address.address_un_data16
#define addr_data8 address.address_un_data8
#ifdef __tile__
/* Atomic Ints performance better on Tile. */
typedef unsigned int FlowRefCount;
#else
typedef unsigned short FlowRefCount;
#endif
#ifdef __tile__
/* Atomic Ints performance better on Tile. */
typedef unsigned int FlowStateType;
#else
typedef unsigned short FlowStateType;
#endif
/** Local Thread ID */
typedef uint16_t FlowThreadId;

@ -1,273 +0,0 @@
/* Copyright (C) 2011-2013 Open Information Security Foundation
*
* You can copy, redistribute or modify this Program under the terms of
* the GNU General Public License version 2 as published by the Free
* Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* version 2 along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
/**
* \file
*
* \author Tom DeCanio <decanio.tom@gmail.com>
* \author Ken Steele, Tilera Corporation <suricata@tilera.com>
*
* Tilera TILE-Gx runmode support
*/
#include "suricata-common.h"
#include "tm-threads.h"
#include "conf.h"
#include "runmodes.h"
#include "runmode-tile.h"
#include "output.h"
#include "source-mpipe.h"
#include "detect-engine.h"
#include "util-debug.h"
#include "util-time.h"
#include "util-cpu.h"
#include "util-affinity.h"
#include "util-device.h"
#ifdef HAVE_MPIPE
/* Number of configured parallel pipelines. */
int tile_num_pipelines;
#endif
/*
* runmode support for tilegx
*/
static const char *mpipe_default_mode = "workers";
const char *RunModeTileMpipeGetDefaultMode(void)
{
return mpipe_default_mode;
}
void RunModeTileMpipeRegister(void)
{
#ifdef HAVE_MPIPE
RunModeRegisterNewRunMode(RUNMODE_TILERA_MPIPE, "workers",
"Workers tilegx mpipe mode, each thread does all"
" tasks from acquisition to logging",
RunModeTileMpipeWorkers);
mpipe_default_mode = "workers";
#endif
}
#ifdef HAVE_MPIPE
void *ParseMpipeConfig(const char *iface)
{
ConfNode *if_root;
ConfNode *mpipe_node;
MpipeIfaceConfig *aconf = SCMalloc(sizeof(*aconf));
char *copymodestr;
char *out_iface = NULL;
if (unlikely(aconf == NULL)) {
return NULL;
}
if (iface == NULL) {
SCFree(aconf);
return NULL;
}
strlcpy(aconf->iface, iface, sizeof(aconf->iface));
/* Find initial node */
mpipe_node = ConfGetNode("mpipe.inputs");
if (mpipe_node == NULL) {
SCLogInfo("Unable to find mpipe config using default value");
return aconf;
}
if_root = ConfNodeLookupKeyValue(mpipe_node, "interface", iface);
if (if_root == NULL) {
SCLogInfo("Unable to find mpipe config for "
"interface %s, using default value",
iface);
return aconf;
}
if (ConfGetChildValue(if_root, "copy-iface", &out_iface) == 1) {
if (strlen(out_iface) > 0) {
aconf->out_iface = out_iface;
}
}
aconf->copy_mode = MPIPE_COPY_MODE_NONE;
if (ConfGetChildValue(if_root, "copy-mode", &copymodestr) == 1) {
if (aconf->out_iface == NULL) {
SCLogInfo("Copy mode activated but no destination"
" iface. Disabling feature");
} else if (strlen(copymodestr) <= 0) {
aconf->out_iface = NULL;
} else if (strcmp(copymodestr, "ips") == 0) {
SCLogInfo("MPIPE IPS mode activated %s->%s",
iface,
aconf->out_iface);
aconf->copy_mode = MPIPE_COPY_MODE_IPS;
} else if (strcmp(copymodestr, "tap") == 0) {
SCLogInfo("MPIPE TAP mode activated %s->%s",
iface,
aconf->out_iface);
aconf->copy_mode = MPIPE_COPY_MODE_TAP;
} else {
SCLogError(SC_ERR_RUNMODE, "Invalid mode (expected tap or ips)");
exit(EXIT_FAILURE);
}
}
return aconf;
}
/**
* \brief RunModeTileMpipeWorkers set up to process all modules in each thread.
*
* \param iface pointer to the name of the interface from which we will
* fetch the packets
* \retval 0 if all goes well. (If any problem is detected the engine will
* exit())
*/
int RunModeTileMpipeWorkers(void)
{
SCEnter();
char tname[TM_THREAD_NAME_MAX];
char *thread_name;
TmModule *tm_module;
int pipe;
RunModeInitialize();
/* Available cpus */
uint16_t ncpus = UtilCpuGetNumProcessorsOnline();
TimeModeSetLive();
unsigned int pipe_max = 1;
if (ncpus > 1)
pipe_max = ncpus - 1;
intmax_t threads;
if (ConfGetInt("mpipe.threads", &threads) == 1) {
tile_num_pipelines = threads;
} else {
tile_num_pipelines = pipe_max;
}
SCLogInfo("%d Tilera worker threads", tile_num_pipelines);
ReceiveMpipeInit();
char *mpipe_dev = NULL;
int nlive = LiveGetDeviceCount();
if (nlive > 0) {
SCLogInfo("Using %d live device(s).", nlive);
/*mpipe_dev = LiveGetDevice(0);*/
} else {
/*
* Attempt to get interface from config file
* overrides -i from command line.
*/
if (ConfGet("mpipe.interface", &mpipe_dev) == 0) {
if (ConfGet("mpipe.single_mpipe_dev", &mpipe_dev) == 0) {
SCLogError(SC_ERR_RUNMODE, "Failed retrieving "
"mpipe.single_mpipe_dev from Conf");
exit(EXIT_FAILURE);
}
}
}
/* Get affinity for worker */
cpu_set_t cpus;
//int result = tmc_cpus_get_my_affinity(&cpus);
int result = tmc_cpus_get_dataplane_cpus(&cpus);
if (result < 0) {
SCLogError(SC_ERR_INVALID_ARGUMENT,
"tmc_cpus_get_my_affinity() returned=%d", result);
SCReturnInt(TM_ECODE_FAILED);
}
for (pipe = 0; pipe < tile_num_pipelines; pipe++) {
char *mpipe_devc;
if (nlive > 0) {
mpipe_devc = SCStrdup("multi");
} else {
mpipe_devc = SCStrdup(mpipe_dev);
}
if (unlikely(mpipe_devc == NULL)) {
printf("ERROR: SCStrdup failed for ReceiveMpipe\n");
exit(EXIT_FAILURE);
}
snprintf(tname, sizeof(tname), "%s#%02d", thread_name_workers, pipe+1);
/* create the threads */
ThreadVars *tv_worker =
TmThreadCreatePacketHandler(tname,
"packetpool", "packetpool",
"packetpool", "packetpool",
"pktacqloop");
if (tv_worker == NULL) {
printf("ERROR: TmThreadsCreate failed\n");
exit(EXIT_FAILURE);
}
tm_module = TmModuleGetByName("ReceiveMpipe");
if (tm_module == NULL) {
printf("ERROR: TmModuleGetByName failed for ReceiveMpipe\n");
exit(EXIT_FAILURE);
}
TmSlotSetFuncAppend(tv_worker, tm_module, (void *)mpipe_devc);
/* Bind to a single cpu. */
int pipe_cpu = tmc_cpus_find_nth_cpu(&cpus, pipe);
tv_worker->rank = pipe;
TmThreadSetCPUAffinity(tv_worker, pipe_cpu);
tm_module = TmModuleGetByName("DecodeMpipe");
if (tm_module == NULL) {
printf("ERROR: TmModuleGetByName DecodeMpipe failed\n");
exit(EXIT_FAILURE);
}
TmSlotSetFuncAppend(tv_worker, tm_module, NULL);
tm_module = TmModuleGetByName("FlowWorker");
if (tm_module == NULL) {
SCLogError(SC_ERR_RUNMODE, "TmModuleGetByName for FlowWorker failed");
exit(EXIT_FAILURE);
}
TmSlotSetFuncAppend(tv_worker, tm_module, NULL);
tm_module = TmModuleGetByName("RespondReject");
if (tm_module == NULL) {
printf("ERROR: TmModuleGetByName for RespondReject failed\n");
exit(EXIT_FAILURE);
}
TmSlotSetFuncAppend(tv_worker, tm_module, NULL);
SetupOutputs(tv_worker);
if (TmThreadSpawn(tv_worker) != TM_ECODE_OK) {
printf("ERROR: TmThreadSpawn failed\n");
exit(EXIT_FAILURE);
}
}
return 0;
}
#endif

@ -1,41 +0,0 @@
/* Copyright (C) 2011-2013 Open Information Security Foundation
*
* You can copy, redistribute or modify this Program under the terms of
* the GNU General Public License version 2 as published by the Free
* Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* version 2 along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
/**
* \file
*
* \author Tom DeCanio <decanio.tom@gmail.com>
* \author Ken Steele, Tilera Corporation <suricata@tilera.com>
*
* Tilera TILE-Gx runmode support
*/
#ifndef __RUNMODE_TILE_H__
#define __RUNMODE_TILE_H__
#include "suricata-common.h"
const char *RunModeTileMpipeGetDefaultMode(void);
void RunModeTileMpipeRegister(void);
extern int tile_num_pipelines;
int RunModeTileMpipeWorkers(void);
void *ParseMpipeConfig(const char *iface);
#endif /* __RUNMODE_TILE_H__ */

@ -135,8 +135,6 @@ static const char *RunModeTranslateModeToName(int runmode)
return "NAPATECH";
case RUNMODE_UNITTEST:
return "UNITTEST";
case RUNMODE_TILERA_MPIPE:
return "MPIPE";
case RUNMODE_AFP_DEV:
return "AF_PACKET_DEV";
case RUNMODE_NETMAP:
@ -224,7 +222,6 @@ void RunModeRegisterRunModes(void)
RunModeIdsAFPRegister();
RunModeIdsNetmapRegister();
RunModeIdsNflogRegister();
RunModeTileMpipeRegister();
RunModeUnixSocketRegister();
RunModeIpsWinDivertRegister();
#ifdef UNITTESTS
@ -317,9 +314,6 @@ void RunModeDispatch(int runmode, const char *custom_mode)
case RUNMODE_DAG:
custom_mode = RunModeErfDagGetDefaultMode();
break;
case RUNMODE_TILERA_MPIPE:
custom_mode = RunModeTileMpipeGetDefaultMode();
break;
case RUNMODE_NAPATECH:
custom_mode = RunModeNapatechGetDefaultMode();
break;

@ -36,7 +36,6 @@ enum RunModes {
RUNMODE_DAG,
RUNMODE_AFP_DEV,
RUNMODE_NETMAP,
RUNMODE_TILERA_MPIPE,
RUNMODE_UNITTEST,
RUNMODE_NAPATECH,
RUNMODE_UNIX_SOCKET,
@ -97,7 +96,6 @@ int RunModeNeedsBypassManager(void);
#include "runmode-pcap.h"
#include "runmode-pcap-file.h"
#include "runmode-pfring.h"
#include "runmode-tile.h"
#include "runmode-nfq.h"
#include "runmode-ipfw.h"
#include "runmode-erf-file.h"

File diff suppressed because it is too large Load Diff

@ -1,93 +0,0 @@
/* Copyright (C) 2011-2013 Open Information Security Foundation
*
* You can copy, redistribute or modify this Program under the terms of
* the GNU General Public License version 2 as published by the Free
* Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* version 2 along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
/**
* \file
*
* \author Tom DeCanio <decanio.tom@gmail.com>
* \author Ken Steele, Tilera Corporation <suricata@tilera.com>
*/
#ifndef __SOURCE_MPIPE_H__
#define __SOURCE_MPIPE_H__
#ifdef HAVE_MPIPE
#include <gxio/mpipe.h>
#include <tmc/cpus.h>
#define MPIPE_FREE_PACKET(p) MpipeFreePacket((p))
#define MPIPE_COPY_MODE_NONE 0
#define MPIPE_COPY_MODE_TAP 1
#define MPIPE_COPY_MODE_IPS 2
#define MPIPE_IFACE_NAME_LENGTH 8
typedef struct MpipeIfaceConfig_
{
char iface[MPIPE_IFACE_NAME_LENGTH];
int copy_mode;
char *out_iface;
} MpipeIfaceConfig;
typedef struct MpipePeer_
{
int channel;
char iface[MPIPE_IFACE_NAME_LENGTH];
} MpipePeer;
/* per interface TAP/IPS configuration */
typedef struct MpipePeerVars_
{
gxio_mpipe_equeue_t *peer_equeue;
void (*ReleasePacket)(struct Packet_ *);
int copy_mode;
} MpipePeerVars;
/* per packet Mpipe vars */
typedef struct MpipePacketVars_
{
/* TileGX mpipe stuff */
struct {
uint_reg_t channel : 5;
uint_reg_t l2_size : 14;
uint_reg_t size : 3;
uint_reg_t bucket_id : 13;
uint_reg_t nr : 1;
uint_reg_t cs : 1;
uint_reg_t va : 42;
uint_reg_t stack_idx : 5;
} idesc;
/* packetpool this was allocated from */
uint8_t rank;
gxio_mpipe_equeue_t *peer_equeue;
} MpipePacketVars;
int MpipeLiveRegisterDevice(char *);
int MpipeLiveGetDeviceCount(void);
char *MpipeLiveGetDevice(int);
void MpipeFreePacket(void *arg);
void TmModuleReceiveMpipeRegister (void);
void TmModuleDecodeMpipeRegister (void);
TmEcode ReceiveMpipeInit(void);
#endif /* HAVE_MPIPE */
#endif /* __SOURCE_MPIPE_H__ */

@ -93,7 +93,6 @@
#include "source-af-packet.h"
#include "source-netmap.h"
#include "source-mpipe.h"
#include "source-windivert.h"
#include "source-windivert-prototypes.h"
@ -654,9 +653,6 @@ static void PrintUsage(const char *progname)
#ifdef BUILD_UNIX_SOCKET
printf("\t--unix-socket[=<file>] : use unix socket to control suricata work\n");
#endif
#ifdef HAVE_MPIPE
printf("\t--mpipe : run with tilegx mpipe interface(s)\n");
#endif
#ifdef WINDIVERT
printf("\t--windivert <filter> : run in inline WinDivert mode\n");
printf("\t--windivert-forward <filter> : run in inline WinDivert mode, as a gateway\n");
@ -772,9 +768,6 @@ static void PrintBuildInfo(void)
#endif
#if defined(__SSE3__)
strlcat(features, "SSE_3 ", sizeof(features));
#endif
#if defined(__tile__)
strlcat(features, "Tilera ", sizeof(features));
#endif
if (strlen(features) == 0) {
strlcat(features, "none", sizeof(features));
@ -887,11 +880,6 @@ void RegisterAllModules(void)
/* pcap file */
TmModuleReceivePcapFileRegister();
TmModuleDecodePcapFileRegister();
#ifdef HAVE_MPIPE
/* mpipe */
TmModuleReceiveMpipeRegister();
TmModuleDecodeMpipeRegister();
#endif
/* af-packet */
TmModuleReceiveAFPRegister();
TmModuleDecodeAFPRegister();
@ -959,21 +947,6 @@ static TmEcode ParseInterfacesList(const int runmode, char *pcap_dev)
SCReturnInt(TM_ECODE_FAILED);
}
}
#ifdef HAVE_MPIPE
} else if (runmode == RUNMODE_TILERA_MPIPE) {
if (strlen(pcap_dev)) {
if (ConfSetFinal("mpipe.single_mpipe_dev", pcap_dev) != 1) {
fprintf(stderr, "ERROR: Failed to set mpipe.single_mpipe_dev\n");
SCReturnInt(TM_ECODE_FAILED);
}
} else {
int ret = LiveBuildDeviceList("mpipe.inputs");
if (ret == 0) {
fprintf(stderr, "ERROR: No interface found in config for mpipe\n");
SCReturnInt(TM_ECODE_FAILED);
}
}
#endif
} else if (runmode == RUNMODE_PFRING) {
/* FIXME add backward compat support */
/* iface has been set on command line */
@ -1531,9 +1504,6 @@ static TmEcode ParseCommandLine(int argc, char** argv, SCInstance *suri)
{"dag", required_argument, 0, 0},
{"napatech", 0, 0, 0},
{"build-info", 0, &build_info, 1},
#ifdef HAVE_MPIPE
{"mpipe", optional_argument, 0, 0},
#endif
#ifdef WINDIVERT
{"windivert", required_argument, 0, 0},
{"windivert-forward", required_argument, 0, 0},
@ -1795,25 +1765,6 @@ static TmEcode ParseCommandLine(int argc, char** argv, SCInstance *suri)
suri->run_mode = RUNMODE_PRINT_BUILDINFO;
return TM_ECODE_OK;
}
#ifdef HAVE_MPIPE
else if(strcmp((long_opts[option_index]).name , "mpipe") == 0) {
if (suri->run_mode == RUNMODE_UNKNOWN) {
suri->run_mode = RUNMODE_TILERA_MPIPE;
if (optarg != NULL) {
memset(suri->pcap_dev, 0, sizeof(suri->pcap_dev));
strlcpy(suri->pcap_dev, optarg,
((strlen(optarg) < sizeof(suri->pcap_dev)) ?
(strlen(optarg) + 1) : sizeof(suri->pcap_dev)));
LiveRegisterDeviceName(optarg);
}
} else {
SCLogError(SC_ERR_MULTIPLE_RUN_MODE,
"more than one run mode has been specified");
PrintUsage(argv[0]);
exit(EXIT_FAILURE);
}
}
#endif
else if(strcmp((long_opts[option_index]).name, "windivert-forward") == 0) {
#ifdef WINDIVERT
if (suri->run_mode == RUNMODE_UNKNOWN) {

@ -1,114 +0,0 @@
/* Copyright (C) 2011-2013 Open Information Security Foundation
*
* You can copy, redistribute or modify this Program under the terms of
* the GNU General Public License version 2 as published by the Free
* Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* version 2 along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
/**
* \file
*
* \author Ken Steele, Tilera Corporation <suricata@tilera.com>
*/
#ifndef __THREADS_ARCH_TILE_H__
#define __THREADS_ARCH_TILE_H__
#include <tmc/spin.h>
#include <arch/cycle.h>
/* NOTE: On Tilera datapath threads use the TMC (Tilera Multicore
* Components) library spin mutexes while the control threads use
* pthread mutexes. So the pthread mutex types are split out so that
* their use can be differentiated.
*/
/* ctrl mutex */
#define SCCtrlMutex pthread_mutex_t
#define SCCtrlMutexAttr pthread_mutexattr_t
#define SCCtrlMutexInit(mut, mutattr ) pthread_mutex_init(mut, mutattr)
#define SCCtrlMutexLock(mut) pthread_mutex_lock(mut)
#define SCCtrlMutexTrylock(mut) pthread_mutex_trylock(mut)
#define SCCtrlMutexUnlock(mut) pthread_mutex_unlock(mut)
#define SCCtrlMutexDestroy pthread_mutex_destroy
/* ctrl cond */
#define SCCtrlCondT pthread_cond_t
#define SCCtrlCondInit pthread_cond_init
#define SCCtrlCondSignal pthread_cond_signal
#define SCCtrlCondTimedwait pthread_cond_timedwait
#define SCCtrlCondWait pthread_cond_wait
#define SCCtrlCondDestroy pthread_cond_destroy
/* mutex */
#define SCMutex tmc_spin_queued_mutex_t
#define SCMutexAttr
#define SCMutexDestroy(x) ({ (void)(x); 0; })
#define SCMUTEX_INITIALIZER TMC_SPIN_QUEUED_MUTEX_INIT
#define SCMutexInit(mut, mutattr) ({ \
int ret = 0; \
tmc_spin_queued_mutex_init(mut); \
ret; \
})
#define SCMutexLock(mut) ({ \
int ret = 0; \
tmc_spin_queued_mutex_lock(mut); \
ret; \
})
#define SCMutexTrylock(mut) ({ \
int ret = (tmc_spin_queued_mutex_trylock(mut) == 0) ? 0 : EBUSY; \
ret; \
})
#define SCMutexUnlock(mut) ({ \
int ret = 0; \
tmc_spin_queued_mutex_unlock(mut); \
ret; \
})
/* conditions */
/* Ignore signals when using spin locks */
#define SCCondT uint8_t
#define SCCondInit(x,y) ({ 0; })
#define SCCondSignal(x) ({ 0; })
#define SCCondDestroy(x) ({ 0; })
static inline void cycle_sleep(int cycles)
{
uint64_t end = get_cycle_count() + cycles;
while (get_cycle_count() < end)
;
}
#define SCCondWait(x,y) cycle_sleep(300)
/* spinlocks */
#define SCSpinlock tmc_spin_queued_mutex_t
#define SCSpinLock(spin) ({ tmc_spin_queued_mutex_lock(spin); 0; })
#define SCSpinTrylock(spin) (tmc_spin_queued_mutex_trylock(spin) ? EBUSY : 0)
#define SCSpinUnlock(spin) ({ tmc_spin_queued_mutex_unlock(spin); 0; })
#define SCSpinInit(spin, spin_attr) ({ tmc_spin_queued_mutex_init(spin); 0; })
#define SCSpinDestroy(spin) ({ (void)(spin); 0; })
/* rwlocks */
#define SCRWLock tmc_spin_rwlock_t
#define SCRWLockDestroy(x) ({ (void)(x); 0; })
#define SCRWLockInit(rwl, rwlattr ) ({ tmc_spin_rwlock_init(rwl); 0; })
#define SCRWLockWRLock(rwl) ({ tmc_spin_rwlock_wrlock(rwl); 0; })
#define SCRWLockRDLock(rwl) ({ tmc_spin_rwlock_rdlock(rwl); 0; })
#define SCRWLockTryWRLock(rwl) (tmc_spin_rwlock_trywrlock(rwl) ? EBUSY : 0)
#define SCRWLockTryRDLock(rwl) (tmc_spin_rwlock_tryrdlock(rwl) ? EBUSY : 0)
#define SCRWLockUnlock(rwl) ({ tmc_spin_rwlock_unlock(rwl); 0; })
#endif

@ -101,9 +101,7 @@ enum {
//#define DBG_THREADS
#ifdef __tile__
#include "threads-arch-tile.h"
#elif defined DBG_THREADS
#if defined DBG_THREADS
#ifdef PROFILE_LOCKING
#error "Cannot mix DBG_THREADS and PROFILE_LOCKING"
#endif
@ -173,7 +171,7 @@ enum {
#define SCSpinDestroy(spin) pthread_spin_destroy(spin)
#endif /* no spinlocks */
#endif /* __tile__ */
#endif
#if (!defined SCMutex || !defined SCMutexAttr || !defined SCMutexInit || \
!defined SCMutexLock || !defined SCMutexTrylock || \

@ -219,8 +219,6 @@ const char * TmModuleTmmIdToString(TmmId id)
CASE_CODE (TMM_DECODEERFFILE);
CASE_CODE (TMM_RECEIVEERFDAG);
CASE_CODE (TMM_DECODEERFDAG);
CASE_CODE (TMM_RECEIVEMPIPE);
CASE_CODE (TMM_DECODEMPIPE);
CASE_CODE (TMM_RECEIVENAPATECH);
CASE_CODE (TMM_DECODENAPATECH);
CASE_CODE (TMM_RECEIVEAFP);

@ -54,8 +54,6 @@ typedef enum {
TMM_RECEIVENETMAP,
TMM_DECODENETMAP,
TMM_ALERTPCAPINFO,
TMM_RECEIVEMPIPE,
TMM_DECODEMPIPE,
TMM_RECEIVENAPATECH,
TMM_DECODENAPATECH,
TMM_STATSLOGGER,

@ -43,8 +43,7 @@
/* test if we have atomic operations support */
#if (!defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8) || !defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4) || \
!defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2) || !defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1)) && \
!defined(__tile__)
!defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2) || !defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1))
/* Do not have atomic operations support, so implement them with locks. */

@ -180,13 +180,6 @@ void UtilCpuPrintSummary(void)
* \todo We'll have to deal with removig ticks from the extra cpuids inbetween
* 2 calls.
*/
#if defined(__tile__)
#include <arch/cycle.h>
uint64_t UtilCpuGetTicks(void)
{
return get_cycle_count();
}
#else
uint64_t UtilCpuGetTicks(void)
{
uint64_t val;
@ -229,4 +222,3 @@ uint64_t UtilCpuGetTicks(void)
#endif
return val;
}
#endif /* __tile__ */

@ -1,370 +0,0 @@
/* Copyright (C) 2014 Open Information Security Foundation
*
* You can copy, redistribute or modify this Program under the terms of
* the GNU General Public License version 2 as published by the Free
* Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* version 2 along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
/**
* \file
*
* \author Tom DeCanio <decanio.tom@gmail.com>
* \author Ken Steele, Tilera Corporation <suricata@tilera.com>
*
* File-like output for logging on Tilera PCIe cards (TILEncore-Gx)
* add the option to send logs across PCIe and then write the output
* files on the host system.
*
*/
#include <sys/types.h>
#include "suricata-common.h" /* errno.h, string.h, etc. */
#include "tm-modules.h" /* LogFileCtx */
#include "conf.h" /* ConfNode, etc. */
#include "util-atomic.h"
#include "util-logopenfile-tile.h"
#ifdef __tile__
#include <gxio/trio.h>
#include <mde-version.h>
#if MDE_VERSION_CODE >= MDE_VERSION(4,1,0)
#include <gxpci/gxpci.h>
#else
#include <gxpci.h>
#endif
/*
* Tilera trio (PCIe) configuration.
*/
static gxio_trio_context_t trio_context_body;
static gxio_trio_context_t* trio_context = &trio_context_body;
/*
* gxpci contexts used for log relay
*/
static gxpci_context_t gxpci_context_body;
static gxpci_context_t *gxpci_context = &gxpci_context_body;
/* The TRIO index. */
static int trio_index = 0;
/* The queue index of a packet queue. */
static unsigned int queue_index = 0;
/* The local PCIe MAC index. */
static int loc_mac;
/*
* Code for writing files over PCIe to host on Tilera TILEncore PCIe cards.
*/
#define OP_OPEN 1
#define OP_WRITE 2
#define OP_CLOSE 3
/** Maximum number of commands in one PCIe function call */
#define MAX_CMDS_BATCH 64
typedef struct {
uint32_t magic;
uint32_t fileno;
uint32_t op;
uint32_t seq;
uint32_t len;
uint32_t next_offset;
char buf[];
} __attribute__((__packed__)) PcieMsg;
static int gxpci_fileno = 0;
static int pcie_initialized = 0;
/* Allocate a Huge page of memory, registered with Trio, into which
data to be sent over PCIe is written. Each write starts at wc_pos.
*/
static char *log_mem = NULL;
static uint64_t wr_pos; /* write position within log_mem */
static SCMutex raw_mutex __attribute__((aligned(64)));
static SCMutex pcie_mutex __attribute__((aligned(64)));
#define CHECK_SEQ_NUM 1
#ifdef CHECK_SEQ_NUM
static uint32_t raw_seq = 0;
#endif
static uint32_t comps_rcvd = 0;
/* Block of memory registered with PCIe DMA engine as a source for
* PCIe data transfers. Must be <= Huge Page size (16 MB).
* Must be large enough that it can't wrap before first PCIe transfer
* has completed.
*/
#define PCIE_MEMORY_BLOCK_SIZE (4 * 1024 * 1024)
/* Send a buffer over PCIe to Host memory.
* len must be smaller than one Packet Queue transfer block.
* TODO: Check errors
*/
static void TilePcieDMABuf(void *buf, uint32_t len)
{
gxpci_comp_t comp[MAX_CMDS_BATCH];
gxpci_cmd_t cmd;
int result;
int credits;
SCMutexLock(&pcie_mutex);
#ifdef CHECK_SEQ_NUM
((PcieMsg *)buf)->seq = ++raw_seq;
__insn_mf();
#endif
/* Wait for credits to be available for more PCIe writes. */
do {
result = gxpci_get_comps(gxpci_context, comp, 0, MAX_CMDS_BATCH);
if (result) {
if (unlikely(result == GXPCI_ERESET)) {
SCLogInfo("gxpci channel is reset");
return;
} else {
__sync_fetch_and_add(&comps_rcvd, result);
}
}
credits = gxpci_get_cmd_credits(gxpci_context);
if (unlikely(credits == GXPCI_ERESET)) {
SCLogInfo("gxpci channel is reset");
return;
}
} while (credits == 0);
cmd.buffer = buf;
/* Round transfer size up to next host cache-line. This will
* transfer more data, but is more efficient.
*/
cmd.size = (len + (CLS - 1)) & ~(CLS - 1);
__insn_mf();
/* Loop until the command is sent. */
do {
/* Send PCIe command to packet queue from tile to host. */
result = gxpci_pq_t2h_cmd(gxpci_context, &cmd);
if (result == 0)
break;
if (result == GXPCI_ERESET) {
SCLogInfo("gxpci channel is reset");
break;
}
/* Not enough credits to send command? */
if (result == GXPCI_ECREDITS)
continue;
} while (1);
SCMutexUnlock(&pcie_mutex);
}
/* Allocate a buffer for data that can be sent over PCIe. Reserves
* space at the beginning for the Pcie msg. The buffer is allocated
* from a 4MB pool on one huge page. The allocation simply walks
* throught the buffer sequentially. This removes the need to free
* the buffers, as they simply age out.
*/
static PcieMsg *TilePcieAllocateBuffer(size_t size)
{
size += sizeof(PcieMsg);
/* Round up to cache-line size */
size = (size + (CLS - 1)) & ~(CLS - 1);
PcieMsg *pmsg;
SCMutexLock(&raw_mutex);
pmsg = (PcieMsg *)&log_mem[wr_pos];
wr_pos += size;
if (wr_pos > PCIE_MEMORY_BLOCK_SIZE) {
/* Don't have enough space at the end of the memory block, so
* wrap to the start.
*/
pmsg = (PcieMsg *)&log_mem[0];
wr_pos = size;
}
SCMutexUnlock(&raw_mutex);
return pmsg;
}
static void PcieWriteOpen(PcieFile *fp, const char *path, const char append)
{
/* Need space for file name, file mode character and string termination */
const int buffer_size = strlen(path) + 2;
/* Allocate space in the PCIe output buffer */
PcieMsg *p = TilePcieAllocateBuffer(buffer_size);
p->magic = 5555;
p->fileno = fp->fileno;
p->op = OP_OPEN;
p->len = offsetof(PcieMsg, buf);
/* Format is one character Mode, followed by file path. */
p->len += snprintf(p->buf, buffer_size, "%c%s", append, path);
TilePcieDMABuf(p, p->len);
}
static int TilePcieWrite(const char *buffer, int buffer_len, LogFileCtx *log_ctx)
{
PcieFile *fp = log_ctx->pcie_fp;
/* Allocate space in the PCIe output buffer */
PcieMsg *p = TilePcieAllocateBuffer(buffer_len);
p->magic = 5555;
p->fileno = fp->fileno;
p->op = OP_WRITE;
p->len = offsetof(PcieMsg, buf);
p->len += buffer_len;
p->next_offset = 0;
/* Can remove the need for this memcpy later. */
memcpy(p->buf, buffer, buffer_len);
TilePcieDMABuf(p, p->len);
return buffer_len;
}
static PcieFile *TileOpenPcieFpInternal(const char *path, const char append_char)
{
int result;
PcieFile *fp;
/* Only initialize once */
if (SCAtomicCompareAndSwap(&pcie_initialized, 0, 1)) {
SCMutexInit(&raw_mutex, NULL);
SCMutexInit(&pcie_mutex, NULL);
SCLogInfo("Initializing Tile-Gx PCIe index %d / %d, queue: %d",
trio_index, loc_mac, queue_index);
result = gxio_trio_init(trio_context, trio_index);
if (result < 0) {
pcie_initialized = 0;
SCLogError(SC_ERR_PCIE_INIT_FAILED,
"gxio_trio_init() failed: %d: %s",
result, gxio_strerror(result));
return NULL;
}
result = gxpci_init(trio_context, gxpci_context, trio_index, loc_mac);
if (result < 0) {
pcie_initialized = 0;
SCLogError(SC_ERR_PCIE_INIT_FAILED,
"gxpci_init() failed: %d: %s",
result, gxpci_strerror(result));
return NULL;
}
/*
* This indicates that we need to allocate an ASID ourselves,
* instead of using one that is allocated somewhere else.
*/
int asid = GXIO_ASID_NULL;
result = gxpci_open_queue(gxpci_context, asid, GXPCI_PQ_T2H, 0,
queue_index, 0, 0);
if (result < 0) {
pcie_initialized = 0;
SCLogError(SC_ERR_PCIE_INIT_FAILED,
"gxpci_open_queue() failed: %d: %s",
result, gxpci_strerror(result));
return NULL;
}
/*
* Allocate and register data buffer
*/
size_t hugepagesz = tmc_alloc_get_huge_pagesize();
tmc_alloc_t alloc = TMC_ALLOC_INIT;
tmc_alloc_set_huge(&alloc);
tmc_alloc_set_home(&alloc, TMC_ALLOC_HOME_HASH);
tmc_alloc_set_pagesize_exact(&alloc, hugepagesz);
log_mem = tmc_alloc_map(&alloc, hugepagesz);
BUG_ON(PCIE_MEMORY_BLOCK_SIZE > hugepagesz);
result = gxpci_iomem_register(gxpci_context, log_mem, hugepagesz);
if (result < 0) {
pcie_initialized = 0;
SCLogError(SC_ERR_PCIE_INIT_FAILED,
"gxpci_iomem_register() failed: %d: %s",
result, gxpci_strerror(result));
return NULL;
}
}
fp = SCMalloc(sizeof(PcieFile));
if (fp == NULL) {
SCLogError(SC_ERR_PCIE_INIT_FAILED,
"Failed to Allocate memory for PCIe file pointer");
return NULL;
}
/* Sequentially allocate File descriptor numbers. Not currently ever freed */
fp->fileno = SCAtomicFetchAndAdd(&gxpci_fileno, 1);
PcieWriteOpen(fp, path, append_char);
return fp;
}
/** \brief Close a PCIe file
* \param PCIe file desriptor
*/
static void TileClosePcieFp(LogFileCtx *log_ctx)
{
SCLogInfo("Closing Tile-Gx PCIe: %s", log_ctx->filename);
/* TODO: Need to count open files and close when reaches zero. */
SCMutexLock(&pcie_mutex);
if (gxpci_context) {
gxpci_destroy(gxpci_context);
gxpci_context = NULL;
}
SCMutexUnlock(&pcie_mutex);
free(log_ctx->pcie_fp);
}
/** \brief open the indicated file remotely over PCIe to a host
* \param path filesystem path to open
* \param append_setting open file with O_APPEND: "yes" or "no"
* \retval FILE* on success
* \retval NULL on error
*/
PcieFile *TileOpenPcieFp(LogFileCtx *log_ctx, const char *path,
const char *append_setting)
{
PcieFile *ret = NULL;
if (ConfValIsTrue(append_setting)) {
ret = TileOpenPcieFpInternal(path, 'a');
} else {
ret = TileOpenPcieFpInternal(path, 'w');
}
/* Override the default Write and Close functions
* with PCIe Write and Close functions.
*/
log_ctx->Write = TilePcieWrite;
log_ctx->Close = TileClosePcieFp;
if (ret == NULL)
SCLogError(SC_ERR_FOPEN, "Error opening PCIe file: \"%s\": %s",
path, strerror(errno));
return ret;
}
#endif /* __tilegx__ */

@ -1,32 +0,0 @@
/* Copyright (C) 2014 Open Information Security Foundation
*
* You can copy, redistribute or modify this Program under the terms of
* the GNU General Public License version 2 as published by the Free
* Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* version 2 along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
/**
* \file
*
* \author Ken Steele, Tilera Corporation <suricata@tilera.com>
*/
#ifndef __UTIL_LOGOPENFILE_TILE_H__
#define __UTIL_LOGOPENFILE_TILE_H__
#include "util-logopenfile.h" /* LogFileCtx */
PcieFile *TileOpenPcieFp(LogFileCtx *log_ctx, const char *path,
const char *append_setting);
#endif /* __UTIL_LOGOPENFILE_TILE_H__ */

@ -31,7 +31,6 @@
#include "util-byte.h"
#include "util-path.h"
#include "util-logopenfile.h"
#include "util-logopenfile-tile.h"
#if defined(HAVE_SYS_UN_H) && defined(HAVE_SYS_SOCKET_H) && defined(HAVE_SYS_TYPES_H)
#define BUILD_WITH_UNIXSOCKET
@ -296,24 +295,6 @@ SCLogOpenFileFp(const char *path, const char *append_setting, uint32_t mode)
return ret;
}
/** \brief open the indicated file remotely over PCIe to a host
* \param path filesystem path to open
* \param append_setting open file with O_APPEND: "yes" or "no"
* \retval FILE* on success
* \retval NULL on error
*/
static PcieFile *SCLogOpenPcieFp(LogFileCtx *log_ctx, const char *path,
const char *append_setting)
{
#ifndef __tile__
SCLogError(SC_ERR_INVALID_YAML_CONF_ENTRY,
"PCIe logging only supported on Tile-Gx Architecture.");
return NULL;
#else
return TileOpenPcieFp(log_ctx, path, append_setting);
#endif
}
/** \brief open a generic output "log file", which may be a regular file or a socket
* \param conf ConfNode structure for the output section in question
* \param log_ctx Log file context allocated by caller
@ -463,10 +444,6 @@ SCConfLogOpenGeneric(ConfNode *conf,
if (rotate) {
OutputRegisterFileRotationFlag(&log_ctx->rotation_flag);
}
} else if (strcasecmp(filetype, "pcie") == 0) {
log_ctx->pcie_fp = SCLogOpenPcieFp(log_ctx, log_path, append);
if (log_ctx->pcie_fp == NULL)
return -1; // Error already logged by Open...Fp routine
#ifdef HAVE_LIBHIREDIS
} else if (strcasecmp(filetype, "redis") == 0) {
ConfNode *redis_node = ConfNodeLookupChild(conf, "redis");

@ -47,14 +47,6 @@
#include "mm_malloc.h"
#endif
#if defined(__tile__)
/* Need to define __mm_ function alternatives, since these are SSE only.
*/
#include <malloc.h>
#define _mm_malloc(a,b) memalign((b),(a))
#define _mm_free(a) free((a))
#endif /* defined(__tile__) */
SC_ATOMIC_EXTERN(unsigned int, engine_stage);
/* Use this only if you want to debug memory allocation and free()

@ -361,127 +361,6 @@ static inline int SCMemcmpLowercase(const void *s1, const void *s2, size_t len)
return 0;
}
#elif defined(__tile__)
#include <ctype.h>
/* Compare to non-zero sequence of bytes. */
static inline int SCMemcmpNZ(const void *s1, const void *s2, size_t len)
{
uint64_t b1, w1, aligned1;
uint64_t b2, w2, aligned2;
/* Load aligned words containing the beginning of each string.
* These loads don't trigger unaligned events.
*/
w1 = __insn_ldna(s1);
w2 = __insn_ldna(s2);
/* Can't just read next 8 bytes because it might go past the end
* of a page. */
while (len > 8) {
/* Here, the buffer extends into the next word by at least one
* byte, so it is safe to read the next word. Do an aligned
* loads on the next word. Then use the two words to create
* an aligned word from each string. */
b1 = __insn_ldna(s1 + 8);
b2 = __insn_ldna(s2 + 8);
aligned1 = __insn_dblalign(w1, b1, s1);
aligned2 = __insn_dblalign(w2, b2, s2);
if (aligned1 != aligned2)
return 1;
/* Move forward one word (8 bytes) */
w1 = b1;
w2 = b2;
len -= 8;
s1 += 8;
s2 += 8;
}
/* Process the last up-to 8 bytes. */
do {
if (*(char*)s1 != *(char*)s2)
return 1;
s1++;
s2++;
len--;
} while (len);
return 0;
}
/* Compare two sequences of bytes. */
static inline int SCMemcmp(const void *s1, const void *s2, size_t len)
{
if (len == 0)
return 0;
return SCMemcmpNZ(s1, s2, len);
}
/** \brief Convert 8 characters to lower case using SIMD.
* \param Word containing the 8 bytes.
* \return Word containing 8-bytes each converted to lowercase.
*/
static inline uint64_t
vec_tolower(uint64_t cc)
{
/* For Uppercases letters, add 32 to convert to lower case. */
uint64_t less_than_eq_Z = __insn_v1cmpltui (cc, 'Z' + 1);
uint64_t less_than_A = __insn_v1cmpltui (cc, 'A');
uint64_t is_upper = __insn_v1cmpne (less_than_eq_Z, less_than_A);
return __insn_v1add (cc,__insn_v1shli (is_upper, 5));
}
/** \brief compare two buffers in a case insensitive way
* \param s1 buffer already in lowercase
* \param s2 buffer with mixed upper and lowercase
*/
static inline int SCMemcmpLowercase(const void *s1, const void *s2, size_t len)
{
uint64_t b1, w1, aligned1;
uint64_t b2, w2, aligned2;
if (len == 0)
return 0;
/* TODO Check for already aligned cases. To optimize. */
/* Load word containing the beginning of each string.
* These loads don't trigger unaligned events.
*/
w1 = __insn_ldna(s1);
w2 = __insn_ldna(s2);
/* Can't just read next 8 bytes because it might go past the end
* of a page. */
while (len > 8) {
/* Here, the buffer extends into the next word by at least one
* byte, so it is safe to read the next word. Do aligned
* loads on next word. Then use the two words to create an
* aligned word from each string. */
b1 = __insn_ldna(s1 + 8);
b2 = __insn_ldna(s2 + 8);
aligned1 = __insn_dblalign(w1, b1, s1);
aligned2 = vec_tolower(__insn_dblalign(w2, b2, s2));
if (aligned1 != aligned2)
return 1;
/* Move forward one word (8 bytes) */
w1 = b1;
w2 = b2;
len -= 8;
s1 += 8;
s2 += 8;
}
do {
if (*(char*)s1 != tolower(*(char*)s2))
return 1;
s1++;
s2++;
len--;
} while (len);
return 0;
}
#else
/* No SIMD support, fall back to plain memcmp and a home grown lowercase one */

@ -88,9 +88,7 @@ uint32_t FUNC_NAME(const SCACTileSearchCtx *ctx, MpmThreadCtx *mpm_thread_ctx,
size_t index = 0 ;
index = SINDEX(index, state);
state = SLOAD(state_table + index + c);
#ifndef __tile__
if (likely(i+1 < buflen))
#endif
c = xlate[buf[i+1]];
if (unlikely(SCHECK(state))) {
matches = CheckMatch(ctx, pmq, buf, buflen, state, i, matches, mpm_bitarray);

@ -1160,19 +1160,11 @@ void SCACTileDestroyCtx(MpmCtx *mpm_ctx)
#define SCHECK(x) ((x) > 0)
#define BUF_TYPE int32_t
// Extract byte N=0,1,2,3 from x
#ifdef __tile__
#define BYTE0(x) __insn_bfextu(x, 0, 7)
#define BYTE1(x) __insn_bfextu(x, 8, 15)
#define BYTE2(x) __insn_bfextu(x, 16, 23)
#define BYTE3(x) __insn_bfextu(x, 24, 31)
#define EXTRA 0
#else /* fallback */
#define BYTE0(x) (((x) & 0x000000ff) >> 0)
#define BYTE1(x) (((x) & 0x0000ff00) >> 8)
#define BYTE2(x) (((x) & 0x00ff0000) >> 16)
#define BYTE3(x) (((x) & 0xff000000) >> 24)
#define EXTRA 4 // need 4 extra bytes to avoid OOB reads
#endif
static int CheckMatch(const SCACTileSearchCtx *ctx, PrefilterRuleStore *pmq,
const uint8_t *buf, uint32_t buflen,
@ -1206,11 +1198,7 @@ static int CheckMatch(const SCACTileSearchCtx *ctx, PrefilterRuleStore *pmq,
/* Double check case-sensitve match now. */
if (patterns[k] >> 31) {
const uint16_t patlen = pat->patlen;
#ifdef __tile__
if (SCMemcmpNZ(pat->cs, buf_offset - patlen, patlen) != 0) {
#else
if (SCMemcmp(pat->cs, buf_offset - patlen, patlen) != 0) {
#endif
/* Case-sensitive match failed. */
continue;
}
@ -1282,22 +1270,12 @@ uint32_t SCACTileSearchLarge(const SCACTileSearchCtx *ctx, MpmThreadCtx *mpm_thr
* Next state entry has MSB as "match" and 15 LSB bits as next-state index.
*/
// y = 1<<log_mult * (x & (1<<width -1))
#ifdef __tile__
#define SINDEX_INTERNAL(y, x, log_mult, width) \
__insn_bfins(y, x, log_mult, log_mult + (width - 1))
#else
#define SINDEX_INTERNAL(y, x, log_mult, width) \
((1<<log_mult) * (x & ((1<<width) - 1)))
#endif
/* Type of next_state */
#define STYPE int16_t
#ifdef __tile__
// Hint to compiler to expect L2 hit latency for Load int16_t
#define SLOAD(x) __insn_ld2s_L2((STYPE* restrict)(x))
#else
#define SLOAD(x) *(STYPE * restrict)(x)
#endif
#define FUNC_NAME SCACTileSearchSmall256
// y = 256 * (x & 0x7FFF)
@ -1350,13 +1328,6 @@ uint32_t SCACTileSearchLarge(const SCACTileSearchCtx *ctx, MpmThreadCtx *mpm_thr
*/
#undef STYPE
#define STYPE int8_t
// Hint to compiler to expect L2 hit latency for Load int8_t
#ifdef __tile__
#undef SLOAD
#define SLOAD(x) __insn_ld1s_L2((STYPE* restrict)(x))
#else
/* no op for !__tile__ case */
#endif
#undef FUNC_NAME
#undef SINDEX
@ -1490,15 +1461,12 @@ void SCACTilePrintInfo(MpmCtx *mpm_ctx)
/************************** Mpm Registration ***************************/
/**
* \brief Register the aho-corasick mpm for Tilera Tile-Gx processor.
* \brief Register the aho-corasick mpm 'ks' originally developed by
* Ken Steele for Tilera Tile-Gx processor.
*/
void MpmACTileRegister(void)
{
#ifdef __tile__
mpm_table[MPM_AC_KS].name = "ac-tile";
#else
mpm_table[MPM_AC_KS].name = "ac-ks";
#endif
mpm_table[MPM_AC_KS].InitCtx = SCACTileInitCtx;
mpm_table[MPM_AC_KS].InitThreadCtx = SCACTileInitThreadCtx;
mpm_table[MPM_AC_KS].DestroyCtx = SCACTileDestroyCtx;

@ -267,18 +267,10 @@ void MpmInitCtx (MpmCtx *mpm_ctx, uint16_t matcher)
/* MPM matcher to use by default, i.e. when "mpm-algo" is set to "auto".
* If Hyperscan is available, use it. Otherwise, use AC. */
#ifdef BUILD_HYPERSCAN
# define DEFAULT_MPM MPM_HS
# ifdef __tile__
# define DEFAULT_MPM_AC MPM_AC_KS
# else
# define DEFAULT_MPM_AC MPM_AC
# endif
# define DEFAULT_MPM MPM_HS
# define DEFAULT_MPM_AC MPM_AC
#else
# ifdef __tile__
# define DEFAULT_MPM MPM_AC_KS
# else
# define DEFAULT_MPM MPM_AC
# endif
# define DEFAULT_MPM MPM_AC
#endif
void MpmTableSetup(void)

@ -1820,33 +1820,6 @@ napatech:
# a range of streams (e.g. streams: ["0-3"])
streams: ["0-3"]
# Tilera mpipe configuration. for use on Tilera TILE-Gx.
mpipe:
# Load balancing modes: "static", "dynamic", "sticky", or "round-robin".
load-balance: dynamic
# Number of Packets in each ingress packet queue. Must be 128, 512, 2028 or 65536
iqueue-packets: 2048
# List of interfaces we will listen on.
inputs:
- interface: xgbe2
- interface: xgbe3
- interface: xgbe4
# Relative weight of memory for packets of each mPipe buffer size.
stack:
size128: 0
size256: 9
size512: 0
size1024: 0
size1664: 7
size4096: 0
size10386: 0
size16384: 0
##
## Configure Suricata to load Suricata-Update managed rules.
##

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