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Bus: Pack state in struct

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pull/3782/head
Stenzek 2 months ago
parent 8778034bf2
commit e175c84227
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16 changed files with 339 additions and 331 deletions
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4
src/core/achievements.cpp
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@ -796,7 +796,7 @@ uint32_t Achievements::ClientReadMemory(uint32_t address, uint8_t* buffer, uint3
if ((static_cast<u64>(address) + num_bytes) > TOTAL_MEMORY_SIZE) [[unlikely]]
return 0;
const u8* src = (address >= MEMORY_SCRATCHPAD_OFFSET) ? CPU::g_state.scratchpad.data() : Bus::g_ram;
const u8* src = (address >= MEMORY_SCRATCHPAD_OFFSET) ? CPU::g_state.scratchpad.data() : g_bus.ram;
const u32 offset = (address & Bus::RAM_2MB_MASK); // size guarded by check above
switch (num_bytes)
@ -3673,7 +3673,7 @@ void Achievements::RAIntegrationWriteMemoryCallback(uint32_t address, uint8_t* b
// This can be called on the UI thread, so always queue it.
llvm::SmallVector<u8, 16> data(buffer, buffer + num_bytes);
Host::RunOnCoreThread([address, data = std::move(data)]() {
u8* src = (address >= MEMORY_SCRATCHPAD_OFFSET) ? CPU::g_state.scratchpad.data() : Bus::g_ram;
u8* src = (address >= MEMORY_SCRATCHPAD_OFFSET) ? CPU::g_state.scratchpad.data() : g_bus.ram;
const u32 offset = (address & Bus::RAM_2MB_MASK); // size guarded by check above
switch (data.size())

482
src/core/bus.cpp
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File diff suppressed because it is too large Load Diff

44
src/core/bus.h
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@ -112,6 +112,33 @@ enum : u32
inline constexpr size_t FASTMEM_ARENA_SIZE = UINT64_C(0x100000000);
#endif
struct Globals
{
u8* ram; // 2MB-8MB RAM
u8* unprotected_ram; // RAM without page protection, use for debugger access.
u8* bios; // 512K BIOS ROM
u32 ram_size; // Active size of RAM.
u32 ram_mapped_size; // Maximum mapped address for RAM, determined by RAM size register.
u32 ram_mask; // Active address bits for RAM.
std::bitset<RAM_8MB_CODE_PAGE_COUNT> ram_code_bits;
std::array<TickCount, 3> exp1_access_time;
std::array<TickCount, 3> exp2_access_time;
std::array<TickCount, 3> bios_access_time;
std::array<TickCount, 3> cdrom_access_time;
std::array<TickCount, 3> spu_access_time;
void** memory_handlers = nullptr;
void** memory_handlers_isc = nullptr;
};
} // namespace Bus
extern Bus::Globals g_bus;
namespace Bus {
bool AllocateMemory(bool export_shared_memory, Error* error);
void ReleaseMemory();
@ -144,19 +171,6 @@ void* GetFastmemBase(bool isc);
void RemapFastmemViews();
bool CanUseFastmemForAddress(VirtualMemoryAddress address);
extern std::bitset<RAM_8MB_CODE_PAGE_COUNT> g_ram_code_bits;
extern u8* g_ram; // 2MB-8MB RAM
extern u8* g_unprotected_ram; // RAM without page protection, use for debugger access.
extern u32 g_ram_size; // Active size of RAM.
extern u32 g_ram_mapped_size; // Maximum mapped address for RAM, determined by RAM size register.
extern u32 g_ram_mask; // Active address bits for RAM.
extern u8* g_bios; // 512K BIOS ROM
extern std::array<TickCount, 3> g_exp1_access_time;
extern std::array<TickCount, 3> g_exp2_access_time;
extern std::array<TickCount, 3> g_bios_access_time;
extern std::array<TickCount, 3> g_cdrom_access_time;
extern std::array<TickCount, 3> g_spu_access_time;
/// Returns true if the address specified is writable (RAM).
ALWAYS_INLINE bool IsRAMAddress(PhysicalMemoryAddress address)
{
@ -166,13 +180,13 @@ ALWAYS_INLINE bool IsRAMAddress(PhysicalMemoryAddress address)
/// Returns the code page index for a RAM address.
ALWAYS_INLINE u32 GetRAMCodePageIndex(PhysicalMemoryAddress address)
{
return (address & g_ram_mask) >> HOST_PAGE_SHIFT;
return (address & g_bus.ram_mask) >> HOST_PAGE_SHIFT;
}
/// Returns true if the specified page contains code.
ALWAYS_INLINE bool IsRAMCodePage(u32 index)
{
return g_ram_code_bits[index];
return g_bus.ram_code_bits[index];
}
/// Flags a RAM region as code, so we know when to invalidate blocks.

10
src/core/cpu_code_cache.cpp
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@ -553,10 +553,10 @@ bool CPU::CodeCache::IsBlockCodeCurrent(const Block* block)
{
// blocks shouldn't be wrapping..
const PhysicalMemoryAddress phys_addr = VirtualAddressToPhysical(block->pc);
DebugAssert((phys_addr + (sizeof(Instruction) * block->size)) <= Bus::g_ram_size);
DebugAssert((phys_addr + (sizeof(Instruction) * block->size)) <= g_bus.ram_size);
// can just do a straight memcmp..
return (std::memcmp(Bus::g_ram + phys_addr, block->Instructions(), sizeof(Instruction) * block->size) == 0);
return (std::memcmp(g_bus.ram + phys_addr, block->Instructions(), sizeof(Instruction) * block->size) == 0);
}
bool CPU::CodeCache::RevalidateBlock(Block* block)
@ -761,12 +761,12 @@ void CPU::CodeCache::ClearBlocks()
PageFaultHandler::HandlerResult PageFaultHandler::HandlePageFault(void* exception_pc, void* fault_address,
bool is_write)
{
if (Bus::g_ram && static_cast<const u8*>(fault_address) >= Bus::g_ram &&
static_cast<const u8*>(fault_address) < (Bus::g_ram + Bus::RAM_8MB_SIZE))
if (g_bus.ram && static_cast<const u8*>(fault_address) >= g_bus.ram &&
static_cast<const u8*>(fault_address) < (g_bus.ram + Bus::RAM_8MB_SIZE))
{
// Writing to protected RAM.
DebugAssert(is_write);
const u32 guest_address = static_cast<u32>(static_cast<const u8*>(fault_address) - Bus::g_ram);
const u32 guest_address = static_cast<u32>(static_cast<const u8*>(fault_address) - g_bus.ram);
const u32 page_index = Bus::GetRAMCodePageIndex(guest_address);
DEV_LOG("Page fault on protected RAM @ 0x{:08X} (page #{}), invalidating code cache.", guest_address, page_index);
CPU::CodeCache::InvalidateBlocksWithPageIndex(page_index);

2
src/core/cpu_code_cache_private.h
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@ -191,7 +191,7 @@ static_assert(sizeof(LoadstoreBackpatchInfo) == 24);
static inline bool AddressInRAM(VirtualMemoryAddress pc)
{
return VirtualAddressToPhysical(pc) < Bus::g_ram_size;
return VirtualAddressToPhysical(pc) < g_bus.ram_size;
}
struct PageProtectionInfo

64
src/core/cpu_core.cpp
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@ -2831,7 +2831,7 @@ ALWAYS_INLINE_RELEASE bool CPU::DoInstructionRead(PhysicalMemoryAddress address,
if (address < RAM_MIRROR_END)
{
std::memcpy(data, &g_ram[address & g_ram_mask], sizeof(u32) * word_count);
std::memcpy(data, &g_bus.ram[address & g_bus.ram_mask], sizeof(u32) * word_count);
if constexpr (add_ticks)
g_state.pending_ticks += (icache_read ? 1 : RAM_READ_TICKS) * word_count;
@ -2839,9 +2839,9 @@ ALWAYS_INLINE_RELEASE bool CPU::DoInstructionRead(PhysicalMemoryAddress address,
}
else if (address >= BIOS_BASE && address < (BIOS_BASE + BIOS_SIZE))
{
std::memcpy(data, &g_bios[(address - BIOS_BASE) & BIOS_MASK], sizeof(u32) * word_count);
std::memcpy(data, &g_bus.bios[(address - BIOS_BASE) & BIOS_MASK], sizeof(u32) * word_count);
if constexpr (add_ticks)
g_state.pending_ticks += g_bios_access_time[static_cast<u32>(MemoryAccessSize::Word)] * word_count;
g_state.pending_ticks += g_bus.bios_access_time[static_cast<u32>(MemoryAccessSize::Word)] * word_count;
return true;
}
@ -2849,7 +2849,7 @@ ALWAYS_INLINE_RELEASE bool CPU::DoInstructionRead(PhysicalMemoryAddress address,
{
g_pio_device->CodeReadHandler(address & EXP1_MASK, data, word_count);
if constexpr (add_ticks)
g_state.pending_ticks += g_exp1_access_time[static_cast<u32>(MemoryAccessSize::Word)] * word_count;
g_state.pending_ticks += g_bus.exp1_access_time[static_cast<u32>(MemoryAccessSize::Word)] * word_count;
return true;
}
@ -2879,7 +2879,7 @@ TickCount CPU::GetInstructionReadTicks(VirtualMemoryAddress address)
}
else if (address >= BIOS_BASE && address < (BIOS_BASE + BIOS_MIRROR_SIZE))
{
return g_bios_access_time[static_cast<u32>(MemoryAccessSize::Word)];
return g_bus.bios_access_time[static_cast<u32>(MemoryAccessSize::Word)];
}
else
{
@ -2900,7 +2900,7 @@ TickCount CPU::GetICacheFillTicks(VirtualMemoryAddress address)
}
else if (address >= BIOS_BASE && address < (BIOS_BASE + BIOS_MIRROR_SIZE))
{
return g_bios_access_time[static_cast<u32>(MemoryAccessSize::Word)] *
return g_bus.bios_access_time[static_cast<u32>(MemoryAccessSize::Word)] *
((ICACHE_LINE_SIZE - (address & (ICACHE_LINE_SIZE - 1))) / sizeof(u32));
}
else
@ -3190,22 +3190,22 @@ ALWAYS_INLINE bool CPU::DoSafeMemoryAccess(VirtualMemoryAddress address, u32& va
if (address < RAM_MIRROR_END)
{
const u32 offset = address & g_ram_mask;
const u32 offset = address & g_bus.ram_mask;
if constexpr (type == MemoryAccessType::Read)
{
if constexpr (size == MemoryAccessSize::Byte)
{
value = g_unprotected_ram[offset];
value = g_bus.unprotected_ram[offset];
}
else if constexpr (size == MemoryAccessSize::HalfWord)
{
u16 temp;
std::memcpy(&temp, &g_unprotected_ram[offset], sizeof(temp));
std::memcpy(&temp, &g_bus.unprotected_ram[offset], sizeof(temp));
value = ZeroExtend32(temp);
}
else if constexpr (size == MemoryAccessSize::Word)
{
std::memcpy(&value, &g_unprotected_ram[offset], sizeof(u32));
std::memcpy(&value, &g_bus.unprotected_ram[offset], sizeof(u32));
}
}
else
@ -3214,10 +3214,10 @@ ALWAYS_INLINE bool CPU::DoSafeMemoryAccess(VirtualMemoryAddress address, u32& va
if constexpr (size == MemoryAccessSize::Byte)
{
if (g_unprotected_ram[offset] != Truncate8(value))
if (g_bus.unprotected_ram[offset] != Truncate8(value))
{
g_unprotected_ram[offset] = Truncate8(value);
if (g_ram_code_bits[page_index])
g_bus.unprotected_ram[offset] = Truncate8(value);
if (g_bus.ram_code_bits[page_index])
CPU::CodeCache::InvalidateBlocksWithPageIndex(page_index);
}
}
@ -3225,22 +3225,22 @@ ALWAYS_INLINE bool CPU::DoSafeMemoryAccess(VirtualMemoryAddress address, u32& va
{
const u16 new_value = Truncate16(value);
u16 old_value;
std::memcpy(&old_value, &g_unprotected_ram[offset], sizeof(old_value));
std::memcpy(&old_value, &g_bus.unprotected_ram[offset], sizeof(old_value));
if (old_value != new_value)
{
std::memcpy(&g_unprotected_ram[offset], &new_value, sizeof(u16));
if (g_ram_code_bits[page_index])
std::memcpy(&g_bus.unprotected_ram[offset], &new_value, sizeof(u16));
if (g_bus.ram_code_bits[page_index])
CPU::CodeCache::InvalidateBlocksWithPageIndex(page_index);
}
}
else if constexpr (size == MemoryAccessSize::Word)
{
u32 old_value;
std::memcpy(&old_value, &g_unprotected_ram[offset], sizeof(u32));
std::memcpy(&old_value, &g_bus.unprotected_ram[offset], sizeof(u32));
if (old_value != value)
{
std::memcpy(&g_unprotected_ram[offset], &value, sizeof(u32));
if (g_ram_code_bits[page_index])
std::memcpy(&g_bus.unprotected_ram[offset], &value, sizeof(u32));
if (g_bus.ram_code_bits[page_index])
CPU::CodeCache::InvalidateBlocksWithPageIndex(page_index);
}
}
@ -3255,17 +3255,17 @@ ALWAYS_INLINE bool CPU::DoSafeMemoryAccess(VirtualMemoryAddress address, u32& va
const u32 offset = (address & BIOS_MASK);
if constexpr (size == MemoryAccessSize::Byte)
{
value = ZeroExtend32(g_bios[offset]);
value = ZeroExtend32(g_bus.bios[offset]);
}
else if constexpr (size == MemoryAccessSize::HalfWord)
{
u16 halfword;
std::memcpy(&halfword, &g_bios[offset], sizeof(u16));
std::memcpy(&halfword, &g_bus.bios[offset], sizeof(u16));
value = ZeroExtend32(halfword);
}
else
{
std::memcpy(&value, &g_bios[offset], sizeof(u32));
std::memcpy(&value, &g_bus.bios[offset], sizeof(u32));
}
return true;
@ -3369,7 +3369,7 @@ bool CPU::SafeReadMemoryBytes(VirtualMemoryAddress addr, void* data, u32 length)
const u32 seg = (addr >> 29);
if ((seg != 0 && seg != 4 && seg != 5) || (((addr + length) & KSEG_MASK) >= RAM_MIRROR_END) ||
(((addr & g_ram_mask) + length) > g_ram_size))
(((addr & g_bus.ram_mask) + length) > g_bus.ram_size))
{
u8* ptr = static_cast<u8*>(data);
u8* const ptr_end = ptr + length;
@ -3383,7 +3383,7 @@ bool CPU::SafeReadMemoryBytes(VirtualMemoryAddress addr, void* data, u32 length)
}
// Fast path: all in RAM, no wraparound.
std::memcpy(data, &g_ram[addr & g_ram_mask], length);
std::memcpy(data, &g_bus.ram[addr & g_bus.ram_mask], length);
return true;
}
@ -3393,7 +3393,7 @@ bool CPU::SafeWriteMemoryBytes(VirtualMemoryAddress addr, const void* data, u32
const u32 seg = (addr >> 29);
if ((seg != 0 && seg != 4 && seg != 5) || (((addr + length) & KSEG_MASK) >= RAM_MIRROR_END) ||
(((addr & g_ram_mask) + length) > g_ram_size))
(((addr & g_bus.ram_mask) + length) > g_bus.ram_size))
{
const u8* ptr = static_cast<const u8*>(data);
const u8* const ptr_end = ptr + length;
@ -3407,7 +3407,7 @@ bool CPU::SafeWriteMemoryBytes(VirtualMemoryAddress addr, const void* data, u32
}
// Fast path: all in RAM, no wraparound.
std::memcpy(&g_ram[addr & g_ram_mask], data, length);
std::memcpy(&g_bus.ram[addr & g_bus.ram_mask], data, length);
return true;
}
@ -3422,7 +3422,7 @@ bool CPU::SafeZeroMemoryBytes(VirtualMemoryAddress addr, u32 length)
const u32 seg = (addr >> 29);
if ((seg != 0 && seg != 4 && seg != 5) || (((addr + length) & KSEG_MASK) >= RAM_MIRROR_END) ||
(((addr & g_ram_mask) + length) > g_ram_size))
(((addr & g_bus.ram_mask) + length) > g_bus.ram_size))
{
while ((addr & 3u) != 0 && length > 0)
{
@ -3453,7 +3453,7 @@ bool CPU::SafeZeroMemoryBytes(VirtualMemoryAddress addr, u32 length)
}
// Fast path: all in RAM, no wraparound.
std::memset(&g_ram[addr & g_ram_mask], 0, length);
std::memset(&g_bus.ram[addr & g_bus.ram_mask], 0, length);
return true;
}
@ -3471,7 +3471,7 @@ void* CPU::GetDirectReadMemoryPointer(VirtualMemoryAddress address, MemoryAccess
if (read_ticks)
*read_ticks = RAM_READ_TICKS;
return &g_ram[paddr & g_ram_mask];
return &g_bus.ram[paddr & g_bus.ram_mask];
}
if ((paddr & SCRATCHPAD_ADDR_MASK) == SCRATCHPAD_ADDR)
@ -3485,9 +3485,9 @@ void* CPU::GetDirectReadMemoryPointer(VirtualMemoryAddress address, MemoryAccess
if (paddr >= BIOS_BASE && paddr < (BIOS_BASE + BIOS_SIZE))
{
if (read_ticks)
*read_ticks = g_bios_access_time[static_cast<u32>(size)];
*read_ticks = g_bus.bios_access_time[static_cast<u32>(size)];
return &g_bios[paddr & BIOS_MASK];
return &g_bus.bios[paddr & BIOS_MASK];
}
return nullptr;
@ -3504,7 +3504,7 @@ void* CPU::GetDirectWriteMemoryPointer(VirtualMemoryAddress address, MemoryAcces
const PhysicalMemoryAddress paddr = address & KSEG_MASK;
if (paddr < RAM_MIRROR_END)
return &g_ram[paddr & g_ram_mask];
return &g_bus.ram[paddr & g_bus.ram_mask];
if ((paddr & SCRATCHPAD_ADDR_MASK) == SCRATCHPAD_ADDR)
return &g_state.scratchpad[paddr & SCRATCHPAD_OFFSET_MASK];

4
src/core/cpu_pgxp.cpp
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@ -132,7 +132,7 @@ static std::FILE* s_log;
size_t CPU::PGXP::GetMemoryValueCount()
{
return (PGXP_SCRATCH_VALUE_COUNT + (Bus::g_ram_size / 4u));
return (PGXP_SCRATCH_VALUE_COUNT + (g_bus.ram_size / 4u));
}
void CPU::PGXP::Initialize()
@ -307,7 +307,7 @@ ALWAYS_INLINE_RELEASE CPU::PGXPValue* CPU::PGXP::GetPtr(u32 addr)
// Don't worry about >512MB here for performance reasons.
const u32 paddr = (addr & KSEG_MASK);
if (paddr < Bus::RAM_MIRROR_END)
return &s_mem[PGXP_MEM_RAM_OFFSET + ((paddr & Bus::g_ram_mask) >> 2)];
return &s_mem[PGXP_MEM_RAM_OFFSET + ((paddr & g_bus.ram_mask) >> 2)];
else
return nullptr;
}

8
src/core/cpu_recompiler.cpp
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@ -75,7 +75,7 @@ void CPU::Recompiler::Recompiler::BeginBlock()
if (m_block->protection == CodeCache::PageProtectionMode::ManualCheck)
{
DEBUG_LOG("Generate manual protection for PC {:08X}", m_block->pc);
const u8* ram_ptr = Bus::g_ram + VirtualAddressToPhysical(m_block->pc);
const u8* ram_ptr = g_bus.ram + VirtualAddressToPhysical(m_block->pc);
const u8* shadow_ptr = reinterpret_cast<const u8*>(m_block->Instructions());
GenerateBlockProtectCheck(ram_ptr, shadow_ptr, m_block->size * sizeof(Instruction));
}
@ -2410,8 +2410,8 @@ CPU::Recompiler::Recompiler::SpecValue CPU::Recompiler::Recompiler::SpecReadMem(
if (CPU::CodeCache::AddressInRAM(address))
{
u32 ram_offset = address & Bus::g_ram_mask;
std::memcpy(&value, &Bus::g_ram[ram_offset], sizeof(value));
u32 ram_offset = address & g_bus.ram_mask;
std::memcpy(&value, &g_bus.ram[ram_offset], sizeof(value));
return value;
}
@ -2430,7 +2430,7 @@ void CPU::Recompiler::Recompiler::SpecWriteMem(u32 address, SpecValue value)
if ((address & SCRATCHPAD_ADDR_MASK) == SCRATCHPAD_ADDR)
m_speculative_constants.memory.emplace(address, value);
else if (CPU::CodeCache::AddressInRAM(address))
m_speculative_constants.memory.emplace(address & Bus::g_ram_mask, value);
m_speculative_constants.memory.emplace(address & g_bus.ram_mask, value);
}
void CPU::Recompiler::Recompiler::SpecInvalidateMem(VirtualMemoryAddress address)

4
src/core/cpu_recompiler_x64.cpp
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@ -251,9 +251,9 @@ static ZyanStatus ZydisFormatterPrintAddressAbsolute(const ZydisFormatter* forma
#define A(x) static_cast<ZyanU64>(reinterpret_cast<uintptr_t>(x))
if (address >= A(Bus::g_ram) && address < A(Bus::g_ram + Bus::g_ram_size))
if (address >= A(g_bus.ram) && address < A(g_bus.ram + g_bus.ram_size))
{
len = snprintf(buf, sizeof(buf), "g_ram+0x%08X", static_cast<u32>(address - A(Bus::g_ram)));
len = snprintf(buf, sizeof(buf), "g_ram+0x%08X", static_cast<u32>(address - A(g_bus.ram)));
}
else if (address >= A(&g_state.regs) &&
address < A(reinterpret_cast<const u8*>(&g_state.regs) + sizeof(CPU::Registers)))

20
src/core/dma.cpp
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@ -515,7 +515,7 @@ ALWAYS_INLINE_RELEASE bool DMA::CheckForBusError(Channel channel, ChannelState&
u32 size)
{
// Relying on a transfer partially happening at the end of RAM, then hitting a bus error would be pretty silly.
if ((address + size) >= Bus::g_ram_mapped_size) [[unlikely]]
if ((address + size) >= g_bus.ram_mapped_size) [[unlikely]]
{
DEBUG_LOG("DMA bus error on channel {} at address 0x{:08X} size {}", channel, address, size);
cs.channel_control.enable_busy = false;
@ -608,8 +608,8 @@ bool DMA::TransferChannel()
DEBUG_LOG("DMA[{}]: Copying linked list starting at 0x{:08X} to device", channel, current_address);
// Prove to the compiler that nothing's going to modify these.
const u8* const ram_ptr = Bus::g_ram;
const u32 mask = Bus::g_ram_mask;
const u8* const ram_ptr = g_bus.ram;
const u32 mask = g_bus.ram_mask;
const TickCount slice_ticks = GetMaxSliceTicks<channel>(g_settings.dma_max_slice_ticks);
TickCount remaining_ticks = slice_ticks;
@ -790,7 +790,7 @@ void DMA::UnhaltTransfer(void*, TickCount ticks)
template<DMA::Channel channel>
TickCount DMA::TransferMemoryToDevice(u32 address, u32 increment, u32 word_count)
{
const u32 mask = Bus::g_ram_mask;
const u32 mask = g_bus.ram_mask;
#if defined(_DEBUG) || defined(_DEVEL)
if ((address & mask) != address)
DEBUG_LOG("DMA TO {} from masked RAM address 0x{:08X} => 0x{:08X}", channel, address, (address & mask));
@ -798,7 +798,7 @@ TickCount DMA::TransferMemoryToDevice(u32 address, u32 increment, u32 word_count
address &= mask;
const u32* src_pointer = reinterpret_cast<u32*>(Bus::g_ram + address);
const u32* src_pointer = reinterpret_cast<u32*>(g_bus.ram + address);
if (static_cast<s32>(increment) < 0 || ((address + (increment * word_count)) & mask) <= address) [[unlikely]]
{
// Use temp buffer if it's wrapping around
@ -806,7 +806,7 @@ TickCount DMA::TransferMemoryToDevice(u32 address, u32 increment, u32 word_count
s_state.transfer_buffer.resize(word_count);
src_pointer = s_state.transfer_buffer.data();
u8* ram_pointer = Bus::g_ram;
u8* ram_pointer = g_bus.ram;
for (u32 i = 0; i < word_count; i++)
{
std::memcpy(&s_state.transfer_buffer[i], &ram_pointer[address], sizeof(u32));
@ -842,7 +842,7 @@ TickCount DMA::TransferMemoryToDevice(u32 address, u32 increment, u32 word_count
template<DMA::Channel channel>
TickCount DMA::TransferDeviceToMemory(u32 address, u32 increment, u32 word_count)
{
const u32 mask = Bus::g_ram_mask;
const u32 mask = g_bus.ram_mask;
#if defined(_DEBUG) || defined(_DEVEL)
if ((address & mask) != address)
DEBUG_LOG("DMA FROM {} to masked RAM address 0x{:08X} => 0x{:08X}", channel, address, (address & mask));
@ -854,7 +854,7 @@ TickCount DMA::TransferDeviceToMemory(u32 address, u32 increment, u32 word_count
if constexpr (channel == Channel::OTC)
{
// clear ordering table
u8* ram_pointer = Bus::g_ram;
u8* ram_pointer = g_bus.ram;
const u32 word_count_less_1 = word_count - 1;
for (u32 i = 0; i < word_count_less_1; i++)
{
@ -868,7 +868,7 @@ TickCount DMA::TransferDeviceToMemory(u32 address, u32 increment, u32 word_count
return Bus::GetDMARAMTickCount(word_count);
}
u32* dest_pointer = reinterpret_cast<u32*>(&Bus::g_ram[address]);
u32* dest_pointer = reinterpret_cast<u32*>(&g_bus.ram[address]);
if (static_cast<s32>(increment) < 0 || ((address + (increment * word_count)) & mask) <= address) [[unlikely]]
{
// Use temp buffer if it's wrapping around
@ -913,7 +913,7 @@ TickCount DMA::TransferDeviceToMemory(u32 address, u32 increment, u32 word_count
if (dest_pointer == s_state.transfer_buffer.data()) [[unlikely]]
{
u8* ram_pointer = Bus::g_ram;
u8* ram_pointer = g_bus.ram;
for (u32 i = 0; i < word_count; i++)
{
std::memcpy(&ram_pointer[address], &s_state.transfer_buffer[i], sizeof(u32));

2
src/core/gpu.cpp
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@ -939,7 +939,7 @@ void GPU::DMAWrite(const u32* RESTRICT words, u32 address, u32 increment, u32 wo
dump->EndGP0Packet();
}
const u32 mask = Bus::g_ram_mask;
const u32 mask = g_bus.ram_mask;
if (const u32 contig_words = std::min(word_count, s_locals.fifo.GetContiguousSpace()); contig_words > 0)
{
const u32* RESTRICT const contig_words_end = words + contig_words;

8
src/core/system.cpp
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@ -2693,7 +2693,7 @@ bool System::LoadBIOS(bool* using_auto_select, Error* error)
WARNING_LOG("Using an unknown BIOS: {}", BIOS::ImageInfo::GetHashString(s_state.bios_hash));
}
std::memcpy(Bus::g_bios, bios_image->data.data(), Bus::BIOS_SIZE);
std::memcpy(g_bus.bios, bios_image->data.data(), Bus::BIOS_SIZE);
return true;
}
@ -2757,7 +2757,7 @@ bool System::SetBootMode(BootMode new_boot_mode, DiscRegion disc_region, bool* m
{
// Patch BIOS, this sucks.
INFO_LOG("Patching BIOS for fast boot.");
if (!BIOS::PatchBIOSFastBoot(Bus::g_bios, Bus::BIOS_SIZE, s_state.bios_image_info->fastboot_patch))
if (!BIOS::PatchBIOSFastBoot(g_bus.bios, Bus::BIOS_SIZE, s_state.bios_image_info->fastboot_patch))
s_state.boot_mode = BootMode::FullBoot;
}
else
@ -3319,7 +3319,7 @@ bool System::SaveStateToBuffer(SaveStateBuffer* buffer, Error* error, u32 screen
// write data
if (buffer->state_data.empty())
buffer->state_data.resize(GetMaxSaveStateSize(Bus::g_ram_size > Bus::RAM_2MB_SIZE));
buffer->state_data.resize(GetMaxSaveStateSize(g_bus.ram_size > Bus::RAM_2MB_SIZE));
return SaveStateDataToBuffer(buffer->state_data, &buffer->state_size, error);
}
@ -3953,7 +3953,7 @@ bool System::DumpRAM(std::string path, Error* error)
return false;
}
return FileSystem::WriteAtomicRenamedFile(std::move(path), Bus::g_unprotected_ram, Bus::g_ram_size, error);
return FileSystem::WriteAtomicRenamedFile(std::move(path), g_bus.unprotected_ram, g_bus.ram_size, error);
}
bool System::DumpVRAM(std::string path, Error* error)

4
src/duckstation-qt/debuggerwindow.cpp
Unescape Escape View File

@ -657,7 +657,7 @@ void DebuggerWindow::setMemoryViewRegion(Bus::MemoryRegion region)
static constexpr auto edit_ram_callback = [](size_t offset, size_t count) {
// shouldn't happen
if (offset >= Bus::g_ram_size)
if (offset >= g_bus.ram_size)
return;
const u32 start_page = static_cast<u32>(offset) >> HOST_PAGE_SHIFT;
@ -665,7 +665,7 @@ void DebuggerWindow::setMemoryViewRegion(Bus::MemoryRegion region)
Host::RunOnCoreThread([start_page, end_page]() {
for (u32 i = start_page; i <= end_page; i++)
{
if (Bus::g_ram_code_bits[i])
if (g_bus.ram_code_bits[i])
CPU::CodeCache::InvalidateBlocksWithPageIndex(i);
}
});

4
src/duckstation-qt/memoryeditorwindow.cpp
Unescape Escape View File

@ -511,7 +511,7 @@ void MemoryEditorWindow::updateMemoryViewRegion()
static constexpr auto edit_ram_callback = [](size_t offset, size_t count) {
// shouldn't happen
if (offset > Bus::g_ram_size)
if (offset > g_bus.ram_size)
return;
const u32 start_page = static_cast<u32>(offset) >> HOST_PAGE_SHIFT;
@ -519,7 +519,7 @@ void MemoryEditorWindow::updateMemoryViewRegion()
Host::RunOnCoreThread([start_page, end_page]() {
for (u32 i = start_page; i <= end_page; i++)
{
if (Bus::g_ram_code_bits[i])
if (g_bus.ram_code_bits[i])
CPU::CodeCache::InvalidateBlocksWithPageIndex(i);
}
});

4
src/duckstation-qt/memoryscannerwindow.cpp
Unescape Escape View File

@ -96,7 +96,7 @@ MemoryScannerWindow::MemoryScannerWindow() : QWidget()
connectUi();
m_ui.cheatEngineAddress->setText(tr("Address of RAM for HxD Usage: 0x%1")
.arg(reinterpret_cast<qulonglong>(Bus::g_unprotected_ram), 16, 16, QChar('0')));
.arg(reinterpret_cast<qulonglong>(g_bus.unprotected_ram), 16, 16, QChar('0')));
}
MemoryScannerWindow::~MemoryScannerWindow() = default;
@ -149,7 +149,7 @@ void MemoryScannerWindow::connectUi()
if (index == 0)
{
m_ui.scanStartAddress->setText(formatHexValue(0, MemoryAccessSize::Word));
m_ui.scanEndAddress->setText(formatHexValue(Bus::g_ram_size, MemoryAccessSize::Word));
m_ui.scanEndAddress->setText(formatHexValue(g_bus.ram_size, MemoryAccessSize::Word));
}
else if (index == 1)
{

2
src/duckstation-regtest/regtest_host.cpp
Unescape Escape View File

@ -717,7 +717,7 @@ void RegTestHost::DumpSystemStateHashes()
INFO_LOG("Save State Hash: {}",
SHA256Digest::DigestToString(SHA256Digest::GetDigest(state_data.cspan(0, state_data_size))));
INFO_LOG("RAM Hash: {}",
SHA256Digest::DigestToString(SHA256Digest::GetDigest(std::span<const u8>(Bus::g_ram, Bus::g_ram_size))));
SHA256Digest::DigestToString(SHA256Digest::GetDigest(std::span<const u8>(g_bus.ram, g_bus.ram_size))));
INFO_LOG("SPU RAM Hash: {}", SHA256Digest::DigestToString(SHA256Digest::GetDigest(SPU::GetRAM())));
}

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