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@ -9,7 +9,11 @@
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#define GSVECTOR_HAS_FAST_INT_SHUFFLE8 1
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#define GSVECTOR_HAS_SRLV 1
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#ifdef CPU_ARCH_ARM64
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// tbl2 with 128-bit vectors is not in A32.
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#define GSVECTOR_HAS_TBL2 1
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#endif
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class GSVector2;
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class GSVector2i;
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@ -2174,12 +2178,14 @@ public:
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return vgetq_lane_s64(vreinterpretq_s64_s32(v4s), i);
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}
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#ifdef CPU_ARCH_ARM64
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ALWAYS_INLINE GSVector4i tbl2(const GSVector4i& a, const GSVector4i& b, const GSVector4i& idx)
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{
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return GSVector4i(vreinterpretq_s32_u8(
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vqtbx2q_u8(vreinterpretq_u8_s32(v4s), uint8x16x2_t{vreinterpretq_u8_s32(a.v4s), vreinterpretq_u8_s32(b.v4s)},
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vreinterpretq_u8_s32(idx.v4s))));
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}
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#endif
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ALWAYS_INLINE static GSVector4i loadnt(const void* p)
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{
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