CPU: Fix some unlikely-to-be-triggered issues

src/core/cpu_core.cpp

@@ -280,7 +280,7 @@ bool CPU::DoState(StateWrapper& sw)
     g_state.load_delay_reg =
       static_cast<Reg>(std::min(static_cast<u8>(g_state.load_delay_reg), static_cast<u8>(Reg::count)));
     g_state.next_load_delay_reg =
-      static_cast<Reg>(std::min(static_cast<u8>(g_state.load_delay_reg), static_cast<u8>(Reg::count)));
+      static_cast<Reg>(std::min(static_cast<u8>(g_state.next_load_delay_reg), static_cast<u8>(Reg::count)));
   }
 
   sw.Do(&g_state.cache_control.bits);
@@ -444,7 +444,7 @@ void CPU::SetIRQRequest(bool state)
   constexpr u32 bit = (1u << 10);
   const u32 old_cause = g_state.cop0_regs.cause.bits;
   g_state.cop0_regs.cause.bits = (g_state.cop0_regs.cause.bits & ~bit) | (state ? bit : 0u);
-  if (old_cause ^ g_state.cop0_regs.cause.bits && state)
+  if ((old_cause ^ g_state.cop0_regs.cause.bits) && state)
     CheckForPendingInterrupt();
 }
 
@@ -1329,7 +1329,7 @@ restart_instruction:
     {
       const u32 rsVal = ReadReg(inst.i.rs);
       const u32 imm = inst.i.imm_zext32();
-      const u32 new_value = ReadReg(inst.i.rs) ^ imm;
+      const u32 new_value = rsVal ^ imm;
       WriteReg(inst.i.rt, new_value);
 
       if constexpr (pgxp_mode >= PGXPMode::CPU)
@@ -2042,7 +2042,6 @@ restart_instruction:
     }
     break;
 
-      break;
     case InstructionOp::swc0:
     case InstructionOp::swc1:
     case InstructionOp::swc3:

src/core/cpu_pgxp.cpp

@@ -617,7 +617,7 @@ ALWAYS_INLINE_RELEASE CPU::PGXPValue* CPU::PGXP::GetCachedVertex(u32 value)
 {
   const s16 sx = static_cast<s16>(value & 0xFFFFu);
   const s16 sy = static_cast<s16>(value >> 16);
-  return (sx >= -1024 && sx <= 1023 && sy >= -1024 && sy <= 1013) ?
+  return (sx >= -1024 && sx <= 1023 && sy >= -1024 && sy <= 1023) ?
            &s_vertex_cache[(sy + 1024) * VERTEX_CACHE_WIDTH + (sx + 1024)] :
            nullptr;
 }
@@ -1378,7 +1378,7 @@ void CPU::PGXP::CPU_MULT(Instruction instr, u32 rsVal, u32 rtVal)
   PGXPValue& ploVal = g_state.pgxp_gpr[static_cast<u8>(Reg::lo)];
   PGXPValue& phiVal = g_state.pgxp_gpr[static_cast<u8>(Reg::hi)];
   ploVal = prsVal;
-  CopyZIfMissing(ploVal, prsVal);
+  CopyZIfMissing(ploVal, prtVal);
 
   // Z/valid is the same
   phiVal = ploVal;
@@ -1424,7 +1424,7 @@ void CPU::PGXP::CPU_MULTU(Instruction instr, u32 rsVal, u32 rtVal)
   PGXPValue& ploVal = g_state.pgxp_gpr[static_cast<u8>(Reg::lo)];
   PGXPValue& phiVal = g_state.pgxp_gpr[static_cast<u8>(Reg::hi)];
   ploVal = prsVal;
-  CopyZIfMissing(ploVal, prsVal);
+  CopyZIfMissing(ploVal, prtVal);
 
   // Z/valid is the same
   phiVal = ploVal;
@@ -1471,7 +1471,7 @@ void CPU::PGXP::CPU_DIV(Instruction instr, u32 rsVal, u32 rtVal)
   PGXPValue& ploVal = g_state.pgxp_gpr[static_cast<u8>(Reg::lo)];
   PGXPValue& phiVal = g_state.pgxp_gpr[static_cast<u8>(Reg::hi)];
   ploVal = prsVal;
-  CopyZIfMissing(ploVal, prsVal);
+  CopyZIfMissing(ploVal, prtVal);
 
   // Z/valid is the same
   phiVal = ploVal;
@@ -1521,7 +1521,7 @@ void CPU::PGXP::CPU_DIVU(Instruction instr, u32 rsVal, u32 rtVal)
   PGXPValue& ploVal = g_state.pgxp_gpr[static_cast<u8>(Reg::lo)];
   PGXPValue& phiVal = g_state.pgxp_gpr[static_cast<u8>(Reg::hi)];
   ploVal = prsVal;
-  CopyZIfMissing(ploVal, prsVal);
+  CopyZIfMissing(ploVal, prtVal);
 
   // Z/valid is the same
   phiVal = ploVal;
@@ -1740,5 +1740,5 @@ void CPU::PGXP::CPU_MTC0(Instruction instr, u32 rdVal, u32 rtVal)
   PGXPValue& prtVal = ValidateAndGetRtValue(instr, rtVal);
   PGXPValue& prdVal = g_state.pgxp_cop0[static_cast<u8>(instr.r.rd.GetValue())];
   prdVal = prtVal;
-  prtVal.value = rdVal;
+  prdVal.value = rdVal;
 }