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@ -780,28 +780,29 @@ void CPU::ARM64Recompiler::GenerateICacheCheckAndUpdate()
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const auto& ticks_reg = RWARG1;
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const auto& current_tag_reg = RWARG2;
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const auto& existing_tag_reg = RWARG3;
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const auto& fill_ticks_reg = w4;
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const auto& ticks_to_add_reg = w5;
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VirtualMemoryAddress current_pc = m_block->pc & ICACHE_TAG_ADDRESS_MASK;
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const TickCount fill_ticks = GetICacheFillTicks(current_pc);
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if (fill_ticks <= 0)
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return;
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armAsm->ldr(ticks_reg, PTR(&g_state.pending_ticks));
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armEmitMov(armAsm, current_tag_reg, current_pc);
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armEmitMov(armAsm, fill_ticks_reg, fill_ticks);
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for (u32 i = 0; i < m_block->icache_line_count; i++, current_pc += ICACHE_LINE_SIZE)
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{
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const TickCount fill_ticks = GetICacheFillTicks(current_pc);
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if (fill_ticks <= 0)
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continue;
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const u32 line = GetICacheLine(current_pc);
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const u32 offset = OFFSETOF(State, icache_tags) + (line * sizeof(u32));
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Label cache_hit;
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armAsm->ldr(existing_tag_reg, MemOperand(RSTATE, offset));
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armAsm->cmp(existing_tag_reg, current_tag_reg);
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armAsm->b(&cache_hit, eq);
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armAsm->str(current_tag_reg, MemOperand(RSTATE, offset));
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armAsm->add(ticks_reg, ticks_reg, armCheckAddSubConstant(static_cast<u32>(fill_ticks)));
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armAsm->bind(&cache_hit);
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armAsm->cmp(existing_tag_reg, current_tag_reg);
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armAsm->csel(ticks_to_add_reg, fill_ticks_reg, wzr, ne);
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armAsm->add(ticks_reg, ticks_reg, ticks_to_add_reg);
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if (i != (m_block->icache_line_count - 1))
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armAsm->add(current_tag_reg, current_tag_reg, armCheckAddSubConstant(ICACHE_LINE_SIZE));
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