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@ -154,36 +154,36 @@ void GPU_SW::UpdateDisplay()
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const u32 vram_offset_y = m_crtc_state.display_vram_top;
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const u32 display_width = m_crtc_state.display_vram_width;
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const u32 display_height = m_crtc_state.display_vram_height;
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const u32 texture_offset_x = m_crtc_state.display_vram_left - m_crtc_state.regs.X;
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if (IsInterlacedDisplayEnabled())
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{
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const u32 field = GetInterlacedField();
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if (m_GPUSTAT.display_area_color_depth_24)
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{
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CopyOut24Bit(m_crtc_state.regs.X, vram_offset_y + field, m_display_texture_buffer.data() + field * VRAM_WIDTH,
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VRAM_WIDTH, display_width, display_height, true);
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VRAM_WIDTH, display_width + texture_offset_x, display_height, true);
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}
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else
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{
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CopyOut15Bit(m_crtc_state.regs.X, vram_offset_y + field, m_display_texture_buffer.data() + field * VRAM_WIDTH,
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VRAM_WIDTH, display_width, display_height, true);
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VRAM_WIDTH, display_width + texture_offset_x, display_height, true);
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}
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}
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else
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{
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if (m_GPUSTAT.display_area_color_depth_24)
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{
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CopyOut24Bit(m_crtc_state.regs.X, vram_offset_y, m_display_texture_buffer.data(), VRAM_WIDTH, display_width,
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display_height, false);
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CopyOut24Bit(m_crtc_state.regs.X, vram_offset_y, m_display_texture_buffer.data(), VRAM_WIDTH,
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display_width + texture_offset_x, display_height, false);
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}
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else
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{
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CopyOut15Bit(m_crtc_state.regs.X, vram_offset_y, m_display_texture_buffer.data(), VRAM_WIDTH, display_width,
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display_height, false);
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CopyOut15Bit(m_crtc_state.regs.X, vram_offset_y, m_display_texture_buffer.data(), VRAM_WIDTH,
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display_width + texture_offset_x, display_height, false);
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}
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}
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const u32 texture_offset_x = m_crtc_state.display_vram_left - m_crtc_state.regs.X;
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m_host_display->UpdateTexture(m_display_texture.get(), texture_offset_x, 0, display_width, display_height,
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m_host_display->UpdateTexture(m_display_texture.get(), 0, 0, display_width, display_height,
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m_display_texture_buffer.data(), VRAM_WIDTH * sizeof(u32));
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m_host_display->SetDisplayTexture(m_display_texture->GetHandle(), VRAM_WIDTH, VRAM_HEIGHT, texture_offset_x, 0,
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display_width, display_height);
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