From 73136d7dc45e51d0282ca9c494595843c376ecd7 Mon Sep 17 00:00:00 2001
From: Stenzek <stenzek@gmail.com>
Date: Fri, 31 May 2024 20:12:55 +1000
Subject: [PATCH] GPU: Tie idle bit to FIFO emptyness on VRAM write

Fixes Tenga Seiha lockup on boot.
---
 src/core/gpu.cpp | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/src/core/gpu.cpp b/src/core/gpu.cpp
index fdd358e8a..e2c5bedb4 100644
--- a/src/core/gpu.cpp
+++ b/src/core/gpu.cpp
@@ -448,19 +448,13 @@ void GPU::UpdateGPUIdle()
   switch (m_blitter_state)
   {
     case BlitterState::Idle:
+    case BlitterState::DrawingPolyLine:
       m_GPUSTAT.gpu_idle = (m_pending_command_ticks <= 0 && m_fifo.IsEmpty());
       break;
 
     case BlitterState::WritingVRAM:
-      m_GPUSTAT.gpu_idle = false;
-      break;
-
     case BlitterState::ReadingVRAM:
-      m_GPUSTAT.gpu_idle = false;
-      break;
-
-    case BlitterState::DrawingPolyLine:
-      m_GPUSTAT.gpu_idle = false;
+      m_GPUSTAT.gpu_idle = m_fifo.IsEmpty();
       break;
 
     default: