Misc: Use a 128b cache line size on Apple Silicon

Turns out it's not 64 bytes like I assumed. The things you learn.

src/common/types.h

@@ -185,6 +185,13 @@ static constexpr u32 HOST_PAGE_MASK = HOST_PAGE_SIZE - 1;
 static constexpr u32 HOST_PAGE_SHIFT = 12;
 #endif
 
+// Host cache line sizes.
+#if defined(__APPLE__) && defined(__aarch64__)
+static constexpr u32 HOST_CACHE_LINE_SIZE = 128; // Apple Silicon uses 128b cache lines.
+#else
+static constexpr u32 HOST_CACHE_LINE_SIZE = 64; // Everything else is 64b.
+#endif
+
 // Enum class bitwise operators
 #define IMPLEMENT_ENUM_CLASS_BITWISE_OPERATORS(type_)                                                                  \
   ALWAYS_INLINE constexpr type_ operator&(type_ lhs, type_ rhs)                                                        \

src/core/gpu_backend.h

@@ -83,8 +83,8 @@ protected:
   };
 
   FixedHeapArray<u8, COMMAND_QUEUE_SIZE> m_command_fifo_data;
-  alignas(64) std::atomic<u32> m_command_fifo_read_ptr{0};
-  alignas(64) std::atomic<u32> m_command_fifo_write_ptr{0};
+  alignas(HOST_CACHE_LINE_SIZE) std::atomic<u32> m_command_fifo_read_ptr{0};
+  alignas(HOST_CACHE_LINE_SIZE) std::atomic<u32> m_command_fifo_write_ptr{0};
 };
 
 #ifdef _MSC_VER